Advanced EDA technology is a crucial link to the next-generation of system-on-chip design.

At Sequence, we're committed to ongoing innovation in the critical Design Closure technology areas - interconnect modeling, and timing, power and signal integrity analysis and optimization. This commitment has been a core component of our ability to deliver high-value solutions to our customers. One reflection of this effort has been our growing portfolio of patents.

To date Sequence has been issued twenty six patents by the U.S. Patent and Trademark Office.

• US Pat. No. 5901063: System and Method for Extracting Parasitic Impedance from an Integrated Circuit Layout; Issued 5/4/1999
• US Pat. No.6057171: Methods for Determining On-Chip Interconnect Process Parameters; Issued 5/2/2000
• US Pat. No.6291254: Methods for Determining On-Chip Interconnect Process Parameters; Issued 9/18/2001
• US Pat. No.6311312: Method for Modeling A Conductive Semiconductor Substrate; Issued 10/30/2001
• US Pat. No.6312963: Methods for Determining On-Chip Interconnect Process Parameters; Issued 11/6/2001
• US Pat. No.6381730: Method and System for Extraction of Parasitic Interconnect Impedance Including Inductance; Issued 4/30/2002
• US Pat. No.6403389: Methods for Determining On-Chip Sheet Resistivity; Issued 6/11/2002
• US Pat. No.6493648: Method and Apparatus for Logic Synthesis (Inferring Complex Components); Issued 12/10/2002
• US Pat. No.6519755: Method and Apparatus Logic Synthesis With Elaboration; Issued 2/11/2003
• US Pat. No.6574787: Method and Apparatus for Logic Synthesis (Word-Oriented Netlist); Issued 6/3/2003
• US Pat. No.6591407: Method and Apparatus for Interconnect-Driven Optimization of Integrated Circuit Design; Issued 7/8/2003
• US Pat. No.6598209: RTL Power Analysis Using Gate-Level Cell Power Models; Issued 7/22/2003
• US Pat. No.6643831: Method and System for Extraction of Parasitic Interconnect Impedance Including Inductance; Issued 11/4/2003
• US Pat. No.6698006: Method for Balanced- Delay Clock Tree Insertion; Issued 2/24/2004
• US Pat. No.6701505: Circuit Optimization for Minimum Path Timing Violations; Issued 3/2/2004
• US Pat. No.6701507: Method for Determining a Zero-Skew Buffer Insertion Point; Issued 3/2/2004
• US Pat. No.6701506: Method for Match Delay Buffer Insertion; Issued 3/2/2004
• US Pat. No.6754877: Method for Optimal Driver Selection; Issued 6/22/2004
• US Pat. No.6807660: Vectorless Instantaneous Current Estimation; Issued 10/19/2004
• US Pat. No.6901565: RTL Power Analysis Using Gate-Level Cell Power Models; Issued 5/31/2005
• US Pat. No.7003741: Method For Optimal Driver Selection; Issued 2/21/2006
• US Pat. No.7117457: Current Scheduling System And Method For Optimizing Multi-Threshold CMOS Designs ; Issued 10/3/2006
• US Pat. No.7185300: Vectorless Instantaneous Current Estimation; Issued 2/27/2007
• US Pat. No.7222318: Circuit Opimization For Minimum Path Timing Violations; Issued 5/22/2007
• US Pat. No.7222311: Method And Apparatus For Interconnect -Driven Optimization Of Integrated Circuit Design; Issued 5/22/2007

• Pat. No.136000: Methods for Determining On-Chip Interconnect Process Parameters; Issued 11/1/2001