Seminar Program & Time Schedule

1220-1250

Registration

1250-13:10
Opening Remarks
"Corporate Update of Sequence Design and Product Strategy"

Vic Kulkarni
President and CEO
Sequence Design, Inc.

1310-13:55

Keynote Speech
"Technology trend on low-power design for SoC's"

Dr. Kimiyoshi Usami
Professor
Dept .of Information Science and Engineering
Shibaura Institute of Technology University

13:55-14:25

EDA Partner Presentation
"Positioning of CyberWorkBench in ESL Design and its Roadmap"

Satoshi Kojima
Technical Marketing Director
CyberWorkBench Business Promotion Office
Platform Business Management Division
NEC System Technologies, Ltd.

14:25-14:55

PowerTheater : Customer Success Story
"
Platform level power simulation & modeling flow using PowerTheater"

Karthikeyan G.T.
Senior Component Design Engineer
Intel Technology India Pvt. Ltd.

1455-1510

Coffee Break

1510-1540

EDA Partner Presentation
"Advanced Low Power Design with the Common Power Format "

Sadao Suzuki
Sr. Technical Marketing Manager
ASIC Alliance Program, Industry Alliance
Cadence Design Systems, Japan

1540-1610

PowerTheater : Customer Success Story
"How to establish appropriate power analysis environments for SoC's"

Fumihiro Minami
Group Manager, Design Methodology Group
EDA Technology Development Department
Design Solution Division
Toshiba Microelectronics Corporation

1610-1700

Sequence DFP products Update
"Low power Design and Optimization using Sequence Products"

Tom Miller
Vice President and General Manager
Sequence Design, Inc.

1700-1715

Co-Sponsor Presentation
"The latest Opteron processor technology supporting for server and workstation platform of HP"

Hiroyuki Yamano
Senior Manager
Product Marketing, Marketing Business Unit
AMD Japan Ltd.

1715-1730
Q&A and Closing Remarks
1730

Close


Seminar Program and Time Schedule in this document are subject to change without notice.
Copyright© 2007 Sequence Design K.K. All Rights Reserved