SANTA
CLARA, Calif. - January 11, 2006 - EDA technology leader
Sequence Design brings its tools and expertise to the hotbed
of nanoscale and low-power design at the upcoming Electronic
Design and Solution Fair (EDSF) in Yokohama, Japan, where
the conference will revolve around life in the 65nm world.
At EDSF, Jan. 26-27, Sequence director of Japan operations,
Hiroshi Ishikawa, will welcome attendees to the company's
booth 401.
Japan's IC designers lead in the development of highly integrated
chips for a variety of consumer electronics, and the booming
portable and communications markets. All require highly sophisticated
approaches to power management - for portables because battery
life is paramount, and for highly integrated 65nm chips because
excess heat can lead to catastrophic failures.
"Power was a manageable issue at 130nm, very challenging
at 90nm, and an absolute killer at 65nm," according to
Sequence CTO and vice president for advanced development,
Jerry Frenkil. "Only through the combination of advanced
design and manufacturing techniques can power be managed effectively,
allowing Japan's innovative and very important semiconductor
industry to advance to the next generation."
Sequence will exhibit its complete lineup of tools for low-power
design, including PowerTheater™, a complete toolkit
for SoC power analysis and optimization; CoolPower™,
providing physical power optimization for leakage power, and
dynamic power; and CoolTime™, for static and dynamic
power grid analysis and optimization.
In addition, Sequence will be showing its Columbus product
suite, providing unparalleled RLC parasitic extraction accuracy
and versatility to meet design challenges at 90nm and beyond.
Columbus's patented extraction engine delivers the precision
needed to model on-chip variations in today's advanced process
technologies, allowing for the reduction of guardbands and
first-pass silicon success. Columbus offers both gate-level
and device-level extraction capabilities, ensuring integration
into power, reliability and signal integrity flows for standard
cell, custom digital, mixed signal, and analog designs.
Those interested in scheduling a meeting with Sequence during
EDSF may contact Aki Momokawa, ,
or telephone 03-5777-1807. For more information on EDSF: .
About Sequence
Sequence Design accelerates the ability of SoC designers
to bring high-performance, power-aware ICs quickly to market.
Sequence's power and signal- integrity software solutions
give customers the competitive advantage necessary to excel
in aggressive technology markets, despite the demanding complexity
and time-to-market issues of nanometer design. Sequence serves
9 of the top 10 semiconductor companies and over 130 customers
worldwide, in application segments such as consumer, wireless,
mobile computing, multimedia, cell phones, digital cameras,
network-on-chip processors, and other power-sensitive markets.
The company was named by Reed Electronics as one of the top
10 companies to watch in the electronics industry, and was
recently selected as one of high-tech's Top 100 companies
by siliconindia magazine. Sequence has worldwide development
and field-service operations and is privately held. Please
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Low-Power Design Tools To Highlight Japan's EDSF