SANTA CLARA, Calif.--(BUSINESS WIRE)--March 18, 2004--Sequence Design announced today that its Columbus-AMS(TM) Tool for Inductance Modeling has been validated on UMC's 130nm process. Sequence has worked with UMC's engineers to successfully create a series of 130nm test chips designed using Sequence's advanced inductance extraction methodology, which demonstrated good yields and performance.

Parasitic interconnect inductance becomes more prolific on complex 0.13um circuits due to tightly packed clock trees and power grids, which in turn affect performance and yields. Sequence's RLS extraction tools are designed to increase chip performance by 20 percent or more, and to improve yields.

Ken Liou, director of UMC's Design Support division, said, "Sequence's Columbus-AMS inductance-modeling methodology has demonstrated greater success than traditional inductance parasitics approaches. We see this technology as valuable resource for our customers' deep submicron design flows."

According to Sequence's Dr. Rob Mathews, director of technical marketing, first-order yield effects caused by inductance are an issue for silicon, particularly as the industry incorporates copper and low-k processes at 0.13um and below.

"A method for incorporating inductance extraction in the physical design flow is essential," Mathews said. "Due to low-resistance interconnect, two physical design tasks that have to take inductance into consideration early in the process are power and clock planning."

Since the complexity levels of power grids and clock trees are much lower than in-block and block-to-block signal lines, it is possible to use advanced RLC extraction engines, such as Sequence's Columbus-AMS, during the hierarchal planning phase of design (along with partitioning, floorplanning, etc.). This technique complements advanced synthesis tools that are also being enhanced to consider inductance.

Columbus-AMS is a 3-D, RLC extractor for mixed-signal, analog, memory, and full-custom digital designs of 1 million transistors or more. The tool is based on Sequence's award-winning ExtractionStage, a suite of high-performance software tuned for complex, multi-million-gate SoCs and analog/mixed-signal design.

Columbus-AMS Feature Summary

• Accurate inductance, capacitance, and resistance extraction
• Ideal for million-plus transistor, mixed-signal, analog, memory, and custom digital designs
• Integrated into the Cadence Analog Design Environment
• Supports both Calibre and Diva LVS flows
• Easy to set up and use -- configurable for a variety of analog devices
• Eliminate the need to support complex parasitic-extraction rule decks

About Sequence

Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections^(TM) and Mentor Graphics' Open Door^(TM) partnership programs. Additional information is available at sequencedesign.com.