By: Will Ruby - EDAVision Magazine, March 2002

Smoke Signals

Wireless communications have a long history - long before Alexander Graham Bell, human beings communicated without wires. Hand signals have been used from the time of prehistoric hunts to modern combat, marines use a flag communications code, and Native Americans have used smoke signals. Today, wireless communications are at the forefront of technology. Mobile phones have evolved from a simple take-everywhere replacement for a landline phone to a full-featured communications platform with e-mail, text messaging, Web browsing capabilities, and more. Personal digital assistants (PDA's) with built-in wireless links are indispensable for modern corporate 'road warriors'. People are talking about installing wireless home networks over a casual lunch with co-workers and friends.

The evolution of mobile wireless communications from phone replacements to communications platforms carries an enormous impact on the design of integrated circuits (ICs) for these applications. Putting more functionality in the same (or, in many cases, smaller) form factor requires integration of many functional components on the same IC. Digital-signal-processing (DSP) cores, general-purpose processors, large amounts of memory, baseband analog, and now even radio-frequency (RF) circuits are placed on the same silicon - ICs for wireless applications are evolving into Systems-on-a-Chip (SoCs).

With this level of complexity, a different kind of smoke signal is going up - smoke that is coming from these SoCs as excessive power consumption due to ever-increasing complexity overwhelms the best efforts in packaging. The power consumed on a single piece of silicon, or power density, is reaching truly astronomical proportions. As Figure 1 indicates, this power density is approaching that of a nuclear reactor today, and expected to reach that of a rocket nozzle.

One of the basic principles of rocket science says that fuel must be burned up as quickly as possible so as to not waste the energy to lift it along with the rest of the rocket. Battery power, the fuel for mobile wireless communications platforms, however, has to last for as long as possible. Increasing power density and the requirement for long battery life make a low-power design methodology a must for wireless IC design.

As wireless technology becomes more pervasive, semiconductor product development is shifting toward wireless and mobile IC design. Performance and cost are no longer the only primary factors determining the viability of a design - power consumption specifications are also becoming critical. As the design space is forced to consider the impact of power, new design teams have recognized that there is a painful lack of expertise in low-power design.

Power Primer

In order to develop a methodology for low-power design it is important to understanding the basics of power consumption, as well as its impact on design. Figure 2 shows the currents flowing in a CMOS inverter when the input is transitioning. Here, Ic is the current used in charging the output capacitance, Isc is the 'short-circuit' current that flows between the P and the N transistor, and Idc is the steady-state leakage current, or standby power which is consumed even when the input is not switching.

Capacitive switching current, Ic, leads to the following expression for dynamic power for CMOS logic:

Pdynamic = CV2f where

• C is the total switched capacitance (gates and interconnect)
  
• V is the power supply voltage
  
• f is the switching frequency

The implication here is that the fewer times the circuit switches, the smaller the capacitive load, and the lower the power supply voltage - the lower is the power consumption. As the process technology continues to evolve, with sub-100nm designs being started today, the power supply voltages are dropping. However, the complexity of today's designs (i.e. switched capacitive load, C), as well as increasing clock frequencies (f) lead to an overall power increase.

The short-circuit current, Isc, depends on the input transition time for a given logic gate. Although the exact relationship is complex, it is important to remember that the slower the transition time, the larger short-circuit current. This means that using small transistors (or gates) does not always result in lower power, as the transition time may be too slow and cause excessive power consumption, even though the timing requirements are met.

Leakage current, and associated leakage (standby) power consumption has been a 'don't care' - until recently. However, that has changed because leakage power dramatically increases as the process geometry shrinks. As more and more functions are being integrated onto a single chip, and efforts are being spent to reduce the dynamic and short-circuit power, leakage power (and its reduction!) is becoming increasingly important.

Low-Power Design Methodology

A good low-power design methodology must address all components of power dissipation throughout the design process. Indeed, while a low-power design is the ultimate goal, management and control of power consumption must become an integral part of the design flow.

A conceptual representation of a design flow is shown in Figure 3.

A system-level description serves as a specification for hardware design as well as software development. As opposed to behavioral synthesis, advocated by some emerging design automation companies, hardware designers today create the design using the register transfer level (RTL) code in Verilog or VHDL hardware description languages (HDLs). When the RTL description is finalized, the RTL code is taken through RTL synthesis tools and the physical design and verification process to generate the final layout data. The RTL and synthesis flow is in wide use today and is very well understood. A low-power design methodology must therefore fit into and be complementary to this mainstream RTL-synthesis flow in order to be adopted by the design community.

At the higher levels, system and RTL, significant opportunities exist to affect the power consumption of the design. This is illustrated in Figure 4.

At the system and RT levels, these opportunities exist because there are more degrees of freedom to change the design. Looking at the equation for dynamic power, CV2f, one can see that all components can be under designer's control. Capacitance represents hardware complexity: available computing resources, memory and pipeline architecture, as well as portions of the design that have to stay active for a given operation or operating mode. Voltage is no longer a fixed parameter - in order to save power, those sections of the design where performance is not critical may be connected to a lower power supply. Clock frequency is also no longer unique in a complex design - sleep modes, active modes, half-speed modes, clock throttling and partitioning are all means to reducing power consumption.

Short-circuit power consumption at higher levels of abstraction is difficult to estimate. However, if the designer is able to estimate capacitances for global signals from a chip floorplan, then the output buffers driving these signals can be appropriately sized. Even if timing is projected to be met, it is critical to size these buffers appropriately so that the receiving buffers do not draw a large amount of short-circuit power due to excessive signal transition times.

By employing a multiple threshold voltage (Vt) process technology, leakage power can be reduced. At the RT-level, the designer can make appropriate tradeoffs to specify that modules or portions of the design that are not performance-critical can be implemented with high-threshold library cells, reducing the overall leakage power.

Synthesis therefore represents an inflection point in the design flow. It is only before synthesis takes place - at the system and RT levels - that significant power savings may be achieved, before the design is mapped to a physical representation. Following synthesis and physical design, it is important to verify the power consumption; much like timing verification is done prior to tapeout. Power verification ensures that the power budget is met.

Low-Power Methodology Implementation

Requirements for electronic design automation (EDA) tools that would enable designers to effectively estimate and reduce power are clear. Fast, high-capacity detailed analysis at high levels of abstraction, such as RTL, enables designers to understand where the power problem areas are in their designs, and direct power reduction efforts to get the most return for the effort. The same analysis tool can then be used for post-synthesis power verification. Flexible and easy-to-use power reduction tools allow designers to understand the tradeoffs and experiment in order to produce a better design. Interactive high-level design tools enable designers to truly exercise their creativity, in contrast to 'automagic' RTL-to-gates power optimization tools that are difficult to control and offer little predictability in their results. An example of a simple RTL code modification resulting in a 10 to 20 percent power savings is shown in Figure 5.

Here, the datapath inputs, DATA_1 and DATA_2, are isolated using a latch to prevent the entire datapath from toggling if the inputs glitch. This technique results in a 10 to 20 percent power savings for this particular example. However, the modified code on the right is just one way of gating the datapath. Other approaches, such as using logic gates and registers in from of the input signal may also be used. Designing for low power means understanding and applying optimization techniques, as well as evaluating tradeoffs for the actual implementation.

Low-Power Design: It's not Rocket Science

As smoke signals rise from today's "burning" wireless designs, the EDA industry is responding with a robust methodology for low-power design, consisting of high-level power analysis and optimization tools that easily fit into existing design flows.

Will Ruby is director of product management for PowerTheater at Sequence Design, Inc.