Sequence Design - Enabling Power Aware Nanometer SoCs  
 
  Sequence Design Home About Us Solutions News & Events Customers Partners Support Careers Contact Us  

Current Releases
Event Calendar
News
CoolCircuit Newsletter
 
 Sequence, Arithmatica Partner To Advance SoC Low-Power Design
Promise Significant Power Improvements With Combined Approach

SANTA CLARA, Calif. - April 11, 2006 - Sequence Design announces that Arithmatica, Inc. has joined its In-Sequence Technology Partner Program, permitting the two companies to significantly advance SoC low-power design technologies and methods. The In-Sequence Program promotes technology advances for power-aware design flows, modeling accuracy, EDA interoperability and research through the alignment of technology partners and academia.

"Working together lets us ensure SoC designers can efficiently and confidently use both CellMath, for datapath, and PowerTheater, for a variety of intellectual property (IP) blocks and full chip, to achieve significant power improvements," said Tony Curzon Price, Arithmatica CEO.

Arithmatica has introduced version 3.0 of the CellMath datapath design tools, incorporating power-knowledgeable synthesis and an extended Verilog interface capable of specifying robust datapath structures. CellMath version 3.0 users typically reduce power by an additional 10 percent to 20 percent over current results in their complex datapath circuits.

Sequence's PowerTheater is the industry standard for low-power design at RTL where 80 percent of a chip's power budget is set. Capabilities range from early RTL analysis to full-chip power estimation and physically-aware power reduction for today's largest designs. PowerTheater allows users to begin the design process with a firm handle on power budgets - before synthesis, when it is too late for significant power reduction - and perform full chip RTL Power Signoff with verified results that correlate to silicon. Arithmatica is working closely with Sequence on RTL modeling, and at the gate level to "power-certify" their datapath results.

"Power-aware SoC design requires a precise, ongoing collaboration between designers, foundries, and EDA vendors," said Vic Kulkarni, Sequence president and CEO. "We created our In-Sequence program to further this collaboration, and are very pleased to welcome Arithmatica into the program."

Arithmatica is the latest in a series of In-Sequence partnerships, joining a variety of EDA vendors, foundries, IP providers, design services, platform vendors and universities.

For details on In-Sequence, contact Sequence at insequence@sequencedesign.com, or visit http://www.sequencedesign.com/5_partners/5a_partners.html.

About Sequence

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves 9 of the top 10 semiconductor companies and over 130 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. The company was named by Reed Electronics as one of the top 10 companies to watch in the electronics industry, and was recently selected as one of high-tech's Top 100 companies by siliconindia magazine. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.

###
All trademarks mentioned herein are the property of their respective owners.
 
Privacy Policy   |   Terms of Use   |   Site Map  |  ©2006-2007 Sequence Design, Inc. All rights reserved