SANTA CLARA, Calif. - April 30, 2003 - In its first production use of Sequence Design's PhysicalStudio, NEC Electronics America, is reporting first-time silicon success in the design of a 1.6-million-gate SoC.

The majority of the design ran at 160MHz, including a timing-critical microprocessor block, while the rest of the design ran at 80MHz. Built using a mature 0.25-micron process technology, the design required NEC Electronics America to stretch the design methodology to meet the required microprocessor performance.

After achieving maximum results for processor speed using state-of-the-art physical synthesis, NEC Electronics America got additional added value using PhysicalStudio for post-route optimization, which allowed the design team to achieve even higher processor speeds.

"With PhysicalStudio, we were able to achieve 160MHz on a 0.25 micron SoC design," said Wolfgang Roethig, Ph.D., senior design engineering manager, Design Solution Center, NEC Electronics America, Inc. "By using PhysicalStudio to deploy cross-talk-conscious timing optimization on the timing-critical block, we could push the performance to meet the customer's expectations, and saved considerable time and expense by getting first-time silicon working at speed."

"PhysicalStudio customers consistently find that this tool provides accuracy and performance benefits that simply cannot be matched by standard flows," according to Dr. Susheel Chandra, Sequence senior vice president of R&D and product marketing. "PhysicalStudio has the unique advantage of 'knowing' what the new routing will look like, even as it fixes crosstalk errors."

About PhysicalStudio

PhysicalStudio is an electrical design closure solution that resolves timing, signal integrity, voltage drop, and power issues concurrently in a single engine. It is fully interoperable with industry-standard routing tools, permitting existing physical design flows to reach fast, predictable design closure in silicon geometries below 90 nanometers.

PhysicalStudio's feature set includes the following:

• Concurrently Optimizes for Timing, Signal Integrity, Power, and Voltage Drop Objectives
• Prevents and corrects crosstalk induced delay and glitch violations
• Optimizes for static (leakage) and dynamic power
• Analyzes impact of instantaneous voltage drop on timing and signal integrity
• On-chip variation, Inductance analysis for high-end designs
• Route-topology driven post route correction introduces predictability in the design flow
• Hierarchical solution for multi-million gate SoC flows

About Sequence

Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' ConnectionsÔ and Mentor Graphics' Open DoorÔ partnership programs. Additional information is available at sequencedesign.com.