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 Sequence Takes Low-Power Message To Top Korean Designers
Sets Record Attendance Describing Low-Power Tools & Strategies

SANTA CLARA, Calif. - May 9, 2006 - Sequence Design, EDA's power-aware SoC design technology leader, set an attendance record at a recent low-power design seminar in Seoul attended by scores of top designers representing 18 major Korean semiconductor companies. Co-sponsored by HP and Sequence's Korean distributor, DavanTech, the daylong seminar addressed major problems affecting chip design for consumer, mobile, and highly integrated devices. Sequence presentations and invited speakers focused on four areas: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design.

Korea's fast-growing chip design market had 2005 sales of $19 billion, and is gaining market share in power-sensitive applications fueled by global demand for cell phones, Digital Multimedia Broadcasting (DMB), MP3, and digital TV applications.

Professor Hyunchul Shin of the college of engineering sciences, Hanyang University, was the keynote speaker, addressing the challenge of designing large, sub-90nm SoCs for low power. Presenting a highly detailed and technical talk offering insights into numerous strategies for low-power design, Professor Shin concluded that power affects multiple aspects of design, including package cost and reliability. To effectively deal with these issues, designers must be "power-aware" at every step, from architectural exploration to manufacturing, and employ integrated tools and methods to achieve concurrent results with timing, signal integrity, and electromigration.

Sequence CTO, Jerry Frenkil, presented a series of case studies, examining how successful teams have made power integrity a key part of their design flow. "Here in Korea they really get it," Frenkil said. "This is a hotbed of portable design for low-power applications, and Sequence is uniquely positioned to provide EDA solutions in the areas of RTL power analysis and optimization, active and leakage power management, and timing and SI optimization as these designers face sub-90 nm SoC design challenges."

About Sequence

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 130 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. The company was named by Reed Electronics as one of the top 10 companies to watch in the electronics industry, and was recently selected as one of high-tech's Top 100 companies by siliconindia magazine. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.

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