SANTA CLARA, Calif. - May 15, 2007 - Sequence Design is unveiling the EDA industry's most comprehensive suite of tools for power-aware design at this year's DAC with its Design For Power (DFP) Flow, attacking the challenges of low-power design holistically, from RTL to GDS. Customers already employing Sequence's DFP Flow are reporting RTL power reduction of up to 50 percent, a 50 percent speedup in design closure times, and leakage power reduction of up to 1,000X.

Demos of all Sequence products and their implementation in a complete DFP Flow will be available at DAC by advance registration. To register online: http://www.sequencedesign.com/dac-2007/index.htm.

"DFP is a holistic approach to power, enabling power exploration from the architectural level through physical implementation, reducing power while preventing power problems in timing, SI, and power grid design, with exclusive 'silicon-aware' features," said Vic Kulkarni, Sequence president and CEO.

Dazzling DFP DAC Demos

Sequence's DFP Flow comprises PowerTheater for RTL power analysis and reduction, with new PowerTheater-Explorer for power visualization and debug. Accelerated design closure, power reduction, and power-grid integrity is supplied by the company's CoolProducts family, now with power gating analysis and simultaneous switching noise options. The award-winning Columbus extraction engine provides statistical corner parasitics for significantly increased margin in the DFP flow.

• Power Estimation
• Power Reduction
  • Architectural Exploration
  • Silicon-Aware Power Management
  • Wattbotts and Linters Eliminate Wasted Power
• Modal Analysis
• RTL Power Signoff
• Gate-Level Power Verification

• Interactively View, Debug and Reduce Power
  • Hierarchical RTL Source
  • SmartSource Viewer
• Perform Regression Testing
• Create Custom Power Data Analyzers and Utilities

• Power-Grid Integrity
• Design Closure and Signoff with Concurrent Timing and SI
• Power Reduction

• AMS: Full-Custom Extraction to Confidently Model High-Performance Designs
• Turbo: SoC Extraction with Price/Performance Accuracy for Modeling Rails and Signals
• Foundation Technology for Sequence DFP flow