SANTA CLARA, Calif. - June 1, 2005 - Sequence Design is highlighting its power prowess with a system-level to signoff flow at this year's DAC, Booth # 301.

For the first time, a complete flow for power analysis and optimization, including dynamic voltage drop, will be demonstrated that seamlessly integrates with existing tools and methods. This approach to "power-aware" design enables leading-edge SoC designers to reduce time to market and costs by taming runaway power and voltage drop, today's top concerns. In addition to its power portfolio, Sequence will be showing its award-winning lineup of technologies for nanometer RCL extraction.

"We are shifting the playing field for power analysis by moving up a level of abstraction," says Vic Kulkarni, Sequence president and CEO. "Enormous gains in efficiency and accuracy can be had by testing assumptions early, well before silicon."

Sequence Technology Demos at DAC

Sequence will be displaying and providing demos for its complete lineup, including PowerTheater, CoolTime, CoolPower (new product), ESL Power Technology (new product), Columbus-AMS, and Columbus-Turbo. Demos for the following will be available throughout the show:

• Sequence technology for power at ESL (Electronic System Level) including integration with ESL simulation and synthesis tools.
• Low-power RTL block design to perform design tradeoffs, power reduction using low power guidelines and power lint checks.
• Full-chip RTL power profiling and debugging, highlighting architectural decisions and tradeoffs to achieve power targets before synthesis.
• Gate-level power verification and signoff including new technology for power profiling to debug power and enable selection of appropriate cycles for downstream power-integrity analysis.

• Sequence technology for power at ESL (Electronic System Level) including integration with ESL simulation and synthesis tools.
• Low-power RTL block design and full-chip power analysis at RTL and gates.
• Power profiling to enable selection of key cycles for physical power integrity.
• Pre- and post-route analysis of power, static and dynamic voltage drop, timing and signalintegrity analysis in a concurrent analysis engine.
• Pre- and post-route optimization of power (standby and active), dynamic voltage drop, timing, and signal integrity in a concurrent optimization engine.
• Exciting new solutions for MTCMOS power gating, active and leakage power tradeoffs, automated voltage drop optimization, and quicker timing closure on hierarchical designs.

• Power and activity profiling capability to enable selection of correct simulation vectors for power-integrity analysis and optimization.
• Static IR-drop, electromigration and dynamic voltage-drop analysis and debug.
• Voltage-drop aware timing and signal integrity analysis.
• MTCMOS power gating system for advanced leakage power optimization.
• Automatic active and leakage power tradeoffs for optimal power consumption.
• Automatic decoupling capacitor optimization for dynamic voltage drop reduction.
• Timing and signal-integrity closure with unique technology for hierarchical designs (block and top-level optimization).
• Electrical signoff for power, voltage drop, timing and signal integrity post-optimization.

• For high-performance, multi-GHz analog designs, Columbus-AMS features selective modeling, user-controllable parasitic reduction, Smart Probing, and Calibre, Diva, and Assura integration in the Cadence Analog Design Environment.
• For characterizing nanometer cells and IP blocks, Columbus-AMS provides accurate C extraction, even around contacted FETs and other devices, Calibre integration, and Tcl scripting.
• For standard-cell designs, Columbus-Turbo has the capacity and speed needed for modeling power rails and managing signal integrity in Cadence, Synopsys, and Magma place & route flows.

Sequence at DAC 2005

Sequence's theme for this year is "Cool by Design," and in its booth # 301 at DAC 2005,products in a system-level to signoff flow wherein power analysis and optimization are seamlessly integrated at each stage in the user's existing design and implementation flow will be shown and demonstrated. To be added to the list for future DAC announcements from Sequence, interested parties may contact: cpuri@sequencedesign.com.

Sequence will have presentations at the Virage Logic VIP Lounge at 11am daily, and will also be present at Intel's demo floor space. The company will also host a meeting of its Technical Advisory Board on Sunday to welcome new members -- Professor Hyunchal Shin from the school of electrical and computer engineering at Korea's HanYang University; and Dr. Kimiyoshi Usami, an associate professor of electrical engineering at Japan's Shibaura Institute of Technology -- and discuss next-generation low-power design solutions.

About Sequence

Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and power-aware nanometer integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 125 customers the competitive advantage necessary to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 10 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of the ARM/Artisan Connected Community (TM), Cadence Design Systems' Connections(TM), Mentor Graphics' Open Door(TM), and Virage Logic VIP(TM) partnership programs. Additional information is available at sequencedesign.com.