SANTA CLARA, Calif. - June 5, 2008 - PowerArtist, the latest in a long line of technically advanced power-reduction tools from Sequence Design, takes center stage at this year's DAC as the company asks, "What color is your RTL?"

"It's a serious question that SoC designers are grappling with," says Sequence President and CEO Vic Kulkarni. "PowerArtist provides a palette of new RTL power-reduction techniques that lets designers mix, blend and apply just the right touches to create their own masterpiece."

PowerArtist focuses on trimming power in three key areas: Clock, Memory, and Datapath at RTL where designers have maximum opportunities for power reduction. The power savings are over and above those achieved during synthesis. Next-generation engines examine the RTL code, prioritize power reductions, and either maximize power savings automatically or guide the user through manual edits within a powerful graphical environment, Sequence's new PowerCanvas™ visualization and debug environment. The RTL changes preserve the original RTL formatting by only making precise, surgical changes to the code.

Demos of all Sequence products and their implementation in a complete DFP Flow will be available at DAC by advance registration. To register online: http://www.sequencedesign.com/dac-2008/registration.php.

Design For Power With Sequence!
Sequence CTO Jerry Frenkil will present a low-power DAC design tutorial on Wednesday, June 11 at 3:20pm. His talk will describe best practices for reducing power at all points in the design flow. For more information: http://www.dac.com/events/eventdetails.aspx?id=77-203

Sequence's DFP (Design For Power) ™ Flow comprises PowerTheater for RTL power analysis and reduction, with PowerTheater-Explorer for power visualization and debug. Accelerated design closure, power reduction, and power-grid integrity is supplied by the company's CoolProducts family, now with power gating analysis and simultaneous switching noise options. The award-winning Columbus extraction engine provides statistical corner parasitics for significantly increased margin in the DFP flow.

Also new this year is formal rail verification that helps to eliminate structural errors in power rails early during implementation, and RTL-driven dynamic Voltage drop analysis that pinpoints power-related functional and test problems. And Columbus solves tough parasitic-modeling problems in custom designs with accurate, simulation-efficient parasitics for analog/mixed-signal and custom digital designs; accurate rail models for EM; formal verification of rails; and graphical analysis and debug of EM and Voltage Drop.