SANTA CLARA, Calif. - June 30, 2003 - Sequence Design will host a low-power design seminar in Tokyo on Friday, July 4, from 1pm to 4:30pm. The event is co-sponsored by Sun Microsystems.

Presentations will focus on methodologies to analyze and optimize power at the RTL level, along with a demonstration of Sequence’s PowerTheater tool suite. In addition, an overview of techniques to reduce SoC leakage power and voltage drop will be discussed. Sequence has held more than 10 seminars dedicated to low-power design methodology since it launched its NanoCool© initiative about a year ago.

Sequence is honored to have guest speakers from Toshiba and Ricoh presenting results of their own low-power design efforts, and the seminar will conclude with an executive briefing detailing future challenges in this area, and the types of EDA tools being designed to deal with them.

“There is little doubt that design success in this decade will be tied directly to a company’s ability to manage power consumption effectively,” according to Vic Kulkarni, Sequence president and CEO. “With its deep consumer electronics and portable computing experience, Japan is positioned to play a leadership role in this new era of 'power-aware' design.”

The seminar will take place at the World Trade Center Bldg. 38F “Sky Hall,” Tokyo, Japan. For additional information please contact afujinawa@sequencedesign.com. Those interested in scheduling similar seminars may contact Sequence at: enquiry@sequencedesign.com.

NanoCool Initiative

Sequence has assembled the elements of a low-power/low-voltage flow spanning architectural, logical, and physical design to respond to the challenges of nanometer design under its NanoCool initiative, a partnership between semiconductor designers, EDA tool vendors, IP companies, and library suppliers, to offer a complete flow linking power management together with timing and signal integrity for rapid design closure.

The initiative has produced a low power/low voltage design flow capable of identifying potential problems caused by power consumption and power distribution, fixing them, and validating the fixes before tape out.

Sequence's leadership position in power, noise and timing optimization, and high accuracy extraction form the foundation for this initiative. On top of this foundation Sequence is building the next generation of EDA capabilities which are specifically targeted at low-voltage, nanometer problems such as minimization of both dynamic and leakage currents, noise margin analysis and optimization, and reliability verification. The overall focus of Sequence's efforts is the concurrent analysis and optimization of power, timing, and noise. The initiative includes both high-level prediction and optimization, coupled with successive refinements and optimizations at lower levels to help designers achieve design closure.

The key components of the NanoCool flow are:

• Architectural Exploration for Power Reduction
• IP Power Modeling
• Vectorless Power Analysis
• Power Grid Design, Analysis and Verification
• Dynamic Power Reduction
• Leakage Power Reduction
• Reliability Analysis
• Noise Margin Analysis
• Advanced Delay Calculation & STA, including noise & coupling (in ShowTime)

About Sequence

Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence’s power and signal integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.er design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems’ Connections^TM and Mentor Graphics’ Open Door^TM partnership programs. Additional information is available at sequencedesign.com.