| SANTA
CLARA, Calif. - February 7, 2008 - Sequence Design today announced
that its flagship low-power design tool, PowerTheater, has
been employed by Atheros Communications for early power management
and low-power architecture evaluation in the development of
new embedded wireless designs.
Atheros, a leading developer of advanced wireless and wired
solutions, uses several elements of the PowerTheater solution
to predict and estimate potential power savings during various
phases of the chip development process. Atheros' expertise
in low power design using advanced techniques in clock- and
data-gating, multi-Vt selection, and voltage islands is enhanced
by PowerTheater. This tool provides early power analysis at
RTL and architectural guidance to enable power efficiencies.
It also features automated Wattbots and power linting capabilities
that evaluate new designs using a set of power rules, and
then provides recommendations for further power reductions.
"Analyzing power at every phase of the design process
is important to the chip performance. The PowerTheater solution
helps guide our architectural decisions early in RTL development
of the chip design process," said Patrick Chan, low power
architect for Atheros. "Atheros' focus on design detail
has enabled us to achieve breakthrough low power, giving our
customers significant competitive advantage."
About PowerTheater/PowerTheater-Explorer
PowerTheater is the industry's first RTL power analysis
and management solution with the singular ability to accurately
estimate and reduce power at RTL and support power management
techniques such as voltage islands, mixed voltage threshold,
power gating, and clock gating. PowerTheater recently added
support for the Si2 CPF standard along with the following
new features:
- Control all aspects of running PowerTheater through a
single Tcl-based command file.
- Identify high power windows utilizing comprehensive simulations
from hardware accelerators.
- Compute full-chip, gate-level power efficiently using
RTL simulations.
- Prevent voltage-drop related test and functional failures
by automatically identifying critical vectors from multiple
simulations.
PowerTheater-Explorer is an innovative option that adds state-of-the
art power visualization and debug capabilities for fast, interactive
power reduction. A new SmartSource Viewer allows designers to
determine hot spots in the design, to visualize, debug and interactively
determine ways to reduce a design's power. The hierarchical
RTL power tree display shows hot spots that can be cross-probed
to schematics, showing connectivity and indicating how activity
is moving through the design and how instances impact one another.
These results can be displayed and analyzed at RTL, gate, or
mixed levels of abstraction. SmartSource also provides a dedicated
view of the clock tree for fast isolation and optimization.
For more information, visit: www.sequencedesign.com/solutions/powertheater.php.
About Sequence Design
Sequence Design accelerates the ability of SoC designers to
bring high-performance, power-aware ICs quickly to market. Sequence
Design-For-Power solutions give customers the competitive advantage
necessary to excel in aggressive technology markets. For more
information: www.sequencedesign.com.
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Sequence PowerTheater Design Tool Provides Atheros with Low-Power
Design Advantages