August 19, 2003 (1:07 p.m. EST)

Power dissipation in digital ICs is a "hot" topic at the moment (if you'll forgive the pun). A few weeks ago I penned a column on Apache Design Solutions and their recently announced power analysis tool RedHawk-SDL (where the "SDL" stands for Static, Dynamic, and Inductance).

At that time, I noted that RedHawk SDL was a "power analysis tool on steroids". However, I was also moved to say:

“One slight fly in the ointment (to my mind) is that, although RedHawk-SDL can do a fantastic job analyzing voltage drop effects, feeding these results to the STA tool (PrimeTime) to re-calculate the timing windows is an iterative process. It seems to me that there is a real need for these tools to work concurrently, such that the results from the power/voltage drop analysis are immediately and concurrently used to re-calculate the timing windows so as to see if any violations have occurred and to fix them on-the-fly.”

So you can only imagine my surprise and delight when the guys and gals at Sequence Design dropped me a line to say how wonderful they had found my article. People always start off this way before they either (a) tell me I'm an idiot and I got things completely wrong or (b) I may or may not be an idiot, by some quirk of fate I managed to get things right, but...

Of course it's when we get to the “but ...” that things start to get interesting. With regard to my “fly in the ointment” paragraph, the Sequence folks said: “We at Sequence believe that you have hit the hammer right on the nail.”

The Sequence guys continued: “Analyzing voltage drop is only part of the problem. What you have out there today is a 'plumbers' analysis flow, which means multiple iterations through multiple tools. You have to be able to analyze the impact of voltage drop on timing and signal integrity in concurrence.”

"But where are we to find such a tool," I cried. I should have known better than to worry, because Sequence appears to have the answer to Life, the Universe, and Everything (and don't tell me it's '42' without specifying the number base we're working in). It seems that the lads and lasses at Sequence have recently launched their CoolTime tool for the simultaneous/concurrent analysis of power, instantaneous voltage drop, electromigration, timing and signal integrity under one platform.

As we all know, some EDA vendors are out to dominate the entire design flow from "soup-to-nuts." This can of course offer a number of advantages, but explaining to your boss why you want to trash your existing (horrendously expensive) implementation engines generally isn't considered to be one of them. For this reason, the folks at Sequence are quick to point out that they want us to keep our existing implementation engines (synthesis, place-and-route) and that their solutions for power, voltage drop, electromigration, signal integrity, and timing will just slip right in there.

PowerTheater, PhysicalStudio, and CoolTime

Speaking of "solutions," I then had to wrap my brain around the various Sequence offerings. First of all we have PowerTheater, which you can use to perform full-chip power analysis, power integrity analysis, and evaluate power tradeoffs - all at the RTL level (Sequence says that 80% of your power problems should be fixed before you begin to use synthesis, and I wouldn't argue about this too much). Once you've qualified your RTL, you push it through your existing floorplanning, synthesis, and place engines (the latter two engines often appear as one in these days of physically aware synthesis).

Next you use Sequence's PhysicalStudio, in conjunction with CoolTime, for pre-route power grid analysis and pre-route optimizations. You then use your existing routing engine, after which PhysicalStudio comes to the fore once more for extraction and post-routing optimizations and electrical signoff ... phew!

As the years have passed, I've become increasingly dissatisfied with having to bounce back and forth from one tool to another. When you fix one problem "here" you introduce another "there" but you don't discover this new "gotcha" until you run the appropriate engine. And when you fix the new problem, this tweak could kick of a whole bucketful of new hassles elsewhere (I'm getting too old for all of this).

So the idea of Sequence-style solutions that concurrently deal with power, voltage drop, EM, SI, and timing brings a little tear of gratitude to my eye and makes my lower lip start quivering with emotion. I also like the fact that CoolTime doesn't simply play around with static approximations of time-variant currents. Instead, it performs instantaneous current analysis to incorporate dynamic effects resulting from power-grid capacitance, package inductance, and on-chip decoupling capacitors (apparently these dynamic effects can contribute to as much as 30 percent to 50 percent of the total voltage drop for designs of 130nm and below). Furthermore, CoolTime examines both power and ground networks simultaneously to account for ground-bounce and power grid resonance.

I also like to hear that they can work with designs containing up to 50 million gates (I'm not sure if I believe it without seeing it, but I certainly like to hear it). To be fair, Sequence did offer some hard numbers, saying that they could perform their vector-less dynamic analysis on 2 million gates per hour using a single 64-bit Solaris processor (which I think is pretty good going) and that these numbers were based on a 25 million gate design, which is impressive whichever way you cut it.

And I really appreciate the Sequence attitude that they are aiming for "accuracy," which, in their context, means "achieving closure without false positives or false negatives." YES! Some folks feel like they are receiving some level of "comfort zone" if their analysis is overly pessimistic, but for those of us living in the real world, pessimism just means more iterations until you receive closure (and being overly pessimistic almost invariably has a negative impact on performance one way or another).

The problem is that cell libraries are usually characterized for three "corners" - temperature, voltage, and process - and the worst case characterization is for temperature to be 10% above nominal, voltage to be 10% below nominal, and a 10% process variation. Wow! It's amazing the things work at all. For this reason, Sequence prefers to work with libraries characterized over 5% to 10% in 0.5% increments (I sort of lost track here, but my understanding is that they have a tool that will automatically re-characterize the library for you using your own HSpice simulator, or Sequence will do it for you if you wish).

As usual, there's a lot more to the story than I've presented here, but the best folks to talk to about this would be the guys and gals at Sequence themselves. So why not call them up or email them and say that they got an official "Cool Beans" from Max. They won't have a clue what you're talking about, but it will make me feel good. Until next time, have a good one!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.