SANTA CLARA, Calif. (Business Wire India) – August 24, 2007- Sequence Design, EDA's Design-For-Power (DFP) technology leader, is taking its popular low-power design seminar to Bangalore again on September 19, 2007. The DFP seminar will be held at The Taj Residency, 41/3 M G Road, Bangalore starting at 9AM, and will conclude with a complimentary luncheon. The event is co-sponsored by Sequence and D'gipro, the distributor for Sequence products for the India market.

Sequence presentations and invited speakers will focus on three areas: predicting power consumption early in the design cycle, reduction of switching power consumption, and reduction of leakage power.

1. Vic Kulkarni, President & CEO, Sequence Design: Sequence Design For Power Update and Strategy
2. Keynote: Dr Satya Gupta, VP Engineering, Open Silicon: Power Challenges in Advanced Process Node
3. Anurag Seth, Engineering Group Director - IC Digital, Cadence: Advanced Low Power Design Using CPF
4. Bharadwaj Amurtur, Assistant Professor, IISc Bangalore: Recent Advances in Leakage Management
5. PowerTheater Success Presentation by Indian Semiconductor Company
6. Rahul Prasad, Sr. Manager, Applications and Customer Support, Sequence Design: Sequence DFP Flow
    

Interested parties may register for the seminar via e-mail to Sequence India's Subrata Mukherjee at subratam@sequencedesign.com.

About Sequence

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets. For more information:sequencedesign.com.