| SANTA
CLARA, Calif. - Nov. 2, 2007 - Sequence Design, EDA's Design-For-Power
(DFP) technology leader, continues to excel by adding two
important patents and announcing Sequence CTO Jerry Frenkil
has a featured chapter in a new book about low-power design.
Sequence's two new patents enable greater power reduction
during physical design. U.S. Patent No.7222318, "Circuit
Optimization For Minimum Path Timing Violations," describes
a method to optimize delay insertions for reducing timing
violations. U.S. Patent No.7222311, "Method And Apparatus
For Interconnect-Driven Optimization of Integrated Circuit
Design," enables post-layout optimization of an integrated
circuit, so designers can avoid costly design iteration loops
that require re-synthesis, re-place and re-route. Both patents
target timing optimizations which are used to realize greater
leakage and dynamic power reduction during physical design.
Sequence currently holds 26 U.S. Patents, and Frenkil says
R&D is "focused like a laser beam" on advancing
the company's comprehensive DFP strategy. "Designers
recognize that effective power management is now a necessity,"
Frenkil said. "The Sequence DFP flow gives them the tools
and methodologies they need today to be successful."
Sequence DFP Advantage
During design, the Sequence DFP flow offers:
- Early power analysis at RTL enabling efficient design
for power when such efforts are most effective
- The industry's most comprehensive portfolio of power reduction
and power debug solutions available at RTL that demonstrate
25-50% power savings
- Qualification of simulation vectors for package selection
and power-grid design
During physical implementation, Sequence delivers:
- Accelerated, predictable power closure of large (>800M
transistors) high-performance designs with more than 33%
advantage in time to market
- Reliable power-grid integrity with a comprehensive set
of technologies for a variety of low-power design techniques
- 20-60% leakage power reduction while preserving timing
and signal integrity, achieving time-to-market savings of
7-10 days per SoC block
New Book Features Frenkil
A new book from Springer, "Closing the Power Gap Between
ASIC & Custom, Tools and Techniques for Low-Power Design,"
describes how to achieve low power and energy efficiency in
highly productive design methodologies. Frenkil's chapter, co-authored
with Srini Venkatraman, principal R&D engineer at Sequence,
covers power-gating techniques and methods to control leakage
power. For more information: http://www.springer.com/west/home/generic/search/results?SGWID=4-40109-22-77145813-0
About Sequence Design
Sequence Design accelerates the ability of SoC designers to
bring high-performance, power-aware ICs quickly to market. Sequence
Design-For-Power solutions give customers the competitive advantage
necessary to excel in aggressive technology markets. For more
information: http://www.sequencedesign.com.
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Sequence
Extends Low-Power Leadership: Two New Patents, CTO Frenkil Featured
In New Design Tome