SANTA CLARA, Calif. - Nov. 9, 2006 - Sequence Design, the EDA leader in power-aware SoC design solutions, will host its fourth low-power design seminar in Tokyo on Dec. 7, 2006, from 12:30pm to 5pm. This event is co-sponsored by Cadence, HP, and NEC System Technology. Japanese chip designers in the fast-growing consumer, mobile, and highly integrated device markets are encouraged to attend by contacting Sequence Japan at: hishikawa@sequencedesign.com, or registering online with www.sequencedesign.com/newsevents/low_power_seminar_japan2.php

The seminar, to be held at Tokyo's Conference Square M+, focuses on four areas: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design. In addition to product and technology updates from Sequence, a series of guest speakers will present on low-power design techniques and related topics.

Sequence Design's President and CEO, Vic Kulkarni, will discuss his company's newest "silicon-aware" power-management and optimization technologies for 65nm designs and present a corporate roadmap of new tools for low-power design. Jerry Frenkil, Sequence CTO, will deliver a presentation titled, "Low Power Design from ESL to GDS."

Keynote speaker Nobuyuki Nishiguchi, Vice President and General Manager of STARC, will speak to "The Challenge for Low-Power Design in System LSI," describing how to address low-power issues for designs below 90nm.

Other speakers include Aurangzeb Khan, Cadence's Corporate Vice President, Business Development, who will discuss an integrated approach to power optimization for semiconductor manufacturers; and NEC System Technology Senior Manager, System CAD, System Devices Research Laboratories, Kazutoshi Wakabayashi, describing a "Design Flow using C-based integrated environment CyberWorkBench and Power-Analysis Capability."

In addition, Key Stream Co., Ltd. Senior Engineer, LSI Engineering Dept., Hiroyuki Sakurai, will present his company's evaluation of Sequence's PowerTheater for power analysis; and Renesas Technology Corp. Senior Engineer, Physical Implementation & Signal Integrity, Backend Design Technology Group, DFM & EDA Technology Development Dept., Design Technology Div., Genichi Tanaka, will present a case study of using Sequence's CoolTime for power-integrity analysis.

"Knowledge of the latest low-power-design research and tools are critically important in Japan, recognized as a world leader and innovator in mobile applications and highly integrated SoCs," said Sequence's Kulkarni. "We look forward to sharing the latest insights in this field with our guests, and presenting the newest technology breakthroughs from Sequence along with local case studies from our Japanese customers."

About Sequence

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. The company was named by Reed Electronics as one of the top 10 companies to watch in the electronics industry, and was recently selected as one of high-tech's Top 100 companies by siliconindia magazine. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.