With power becoming a severe bottleneck in high performance nanometer-scale (sub-0.1 micron feature sizes) IC design, there is a strong need for a cohesive and comprehensive power-aware design methodology. Unfortunately, today's ad hoc approaches are insufficient and inefficient. They fail to see the big picture, which is that high-performance design cannot continue to exist without the careful orchestration of all present best-known power reduction techniques.

Designers wrestling with this issue must bear in mind that: 1) power is a first-class citizen, comparable in importance to timing; 2) the design community requires a multi-tiered approach to power, ranging from coarse early-design exploration models to highly accurate final sign-off analysis tools; and 3) power cross-cuts with a number of other key nanometer design issues such as variability and signal integrity.

While we recognize that power poses a fundamental roadblock to the continuation of Moore's law, the breadth of the problem goes largely unacknowledged. Beyond traditional static and dynamic power consumption, there exist further sub-divisions such as subthreshold and gate leakage components, along with active and standby mode leakage. For example, the amount of leakage power in active circuits (it's not just a standby problem) is a growing concern as it bites off increasingly big chunks of the overall power budget as device geometries shrink.

Beyond the need for new approaches to low-power IC design, a more pressing problem is a lack of best-practices in low-power EDA tools. Probably the best example is an integrated approach to multi-Vdd and multi-Vth design. The use of multiple (typically dual) supply and threshold voltages can provide large reductions in power consumption, both dynamic and static. Recent research indicates that total power could be reduced by 60 percent or more using these techniques, yet algorithms to allow for intelligent assignment of Vdd and Vth on a gate-by-gate basis in standard cell designs are not commercially available. While admittedly the research community is still converging towards optimal solutions to this complex problem, the general concept of simultaneous multi-Vdd/Vth design is clearly going to be a big part of the low-power designer's toolbox for the next decade. Tool development here should be an industry focal point; enhancements can then be added on in a relatively straightforward fashion (e.g., more than 2 Vth's, improved algorithms allowing for both synchronous and asynchronous level conversion, etc.).

An ideal EDA low-power suite will include variable accuracy/complexity tools that allow designers to first explore potential options with only coarse knowledge of the overall design characteristics. At the architectural level this could be particularly helpful in DSP applications where the degree of parallelism and a programmable vs. direct-mapped solution can be investigated. As the architecture, logic families, latch/flip-flop, and other decisions are made, the tools become increasingly accurate and complex, considering issues such as cell library granularity, clock gating, power grid topology, and the potential use of sleep modes in the process. Finally, final power sign-off (akin to timing sign-off) will take place. These techniques must inherently address key issues such as thermal gradients across the die, as well as relationships among power, variability, and signal integrity.

On this last point, a key example lies in the exponential dependencies of subthreshold leakage on threshold voltage (Vth) and gate leakage on oxide thickness. Due to the small size of MOSFET conducting channels and the small number of dopant atoms therein, the controllability of Vth is becoming more difficult. Deviations on the order of 20-30mV can lead to a 100 percent or larger increase in subthreshold leakage while a reduction in oxide thickness of just 1 Angstrom (0.1nm) causes gate leakage to more than triple. These dependencies place an incredible burden on process engineers to create controllable processes which then leads to rising development costs and turnaround times. In this way, power can be seen to ultimately affect costs in a strong manner.

The current trends in power consumption for high-performance IC design are truly alarming. Indeed, the changeovers from bipolar, to NMOS, to CMOS have always been dictated by similar power trends. The key to extending the lifespan of CMOS well into the nanoscale realm lies in the continued development of such techniques and their successful integration within commercial EDA flows.