SANTA CLARA, Calif. - Dec. 12, 2006 - Sequence Design, the EDA leader in power-aware SoC design solutions, recently hosted more than 80 Japanese IC designers, representing 23 leading Japanese electronics companies, at its fourth low-power design seminar in Tokyo. Co-sponsored by Cadence, HP, and NEC System Technology, the daylong event addressed major problems affecting chip design for consumer, mobile, and highly integrated devices. The focus was on four areas: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design.

Keynote speaker Nobuyuki Nishiguchi, Vice President and General Manager of STARC, discussed "The Challenge for Low-Power Design in System LSI," describing how to address low-power issues for designs below 90nm. He was joined on the agenda by industry luminaries from Cadence, NEC, and Renesas; and Sequence executives presented their latest tools and technologies for low-power design.

About Sequence

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.