Where are the biggest power savings in advanced designs? What tools and techniques deliver the biggest bang for the buck? Are there things we should be doing differently to maximize power efficiency? Can you show me some real-world success stories?

These are questions I hear a lot during customer visits and at our "Design For Power" (DFP) seminars, so I am sure many of you are wondering about the same things. In the past, design engineers could do little to control and manage power, but with today's tools, a variety of techniques can be used to reduce power 50% or more. Some proven techniques for power reduction include:

• Architectural exploration: because 80% of power is committed before gate implementation
• Power debug environment for user-controlled power reduction
• Automated RTL power linting and advisories
• Power saving techniques such as multi Vt, clock gating, voltage islands and power gating

RTL power analysis using tools such as PowerTheater, with more than 900 successful tapeouts worldwide, is an essential part of a comprehensive power-management design strategy. Our customers have shared the importance of early power analysis at RTL::

Company	Power Reduction	Technique
Chip graphics / multimedia company	Reduced block power by 50%	Architectural exploration early at RTL
Wireless division of well-known fabless company	Reduced block power by 50%	Architectural exploration early at RTL
Processor company	Full chip power reduced by 20%	Architectural exploration early at RTL

Common power management techniques often involve complex tradeoffs in complexity, timing, area, etc. Our experience with these techniques indicates what savings can be expected so designers can determine which techniques provide the best bang for their buck:

Technique	Power Savings
Mixed-Vt	5-15% savings
Clock gating	>25% clock savings
Voltage Islands	10-50% savings
Power Gating	10-1000X leakage savings

Clock gating is one of the most popular and widely used power reduction techniques available today, since clocks are other 30-50% of total chip power. Designers often save more than 25% of total clock power with clock gating. But trade-offs are done between timing, leakage power and area during its implementation. Minimizing the impact of these tradeoffs and further reducing clock power is the goal of an R&D effort within Sequence today, the results of which we hope to share with you soon.

A powerful debug and visualization environment is part of the requirement for DFP , and the new PowerTheater Explorer is the epitome of user-controlled power reduction. Stay tuned for more customer successes in power reduction using this PowerTheater option. Explorer makes power analysis and reduction available across the entire engineerint team, and publishes critical power information accessibly in the OpenAccess standard. Sequence expects to build on this power debug environment with a variety of new reduction tools and solutions.

The chart below shows major power reductions at Sequence customers, in a wide range of applications:

Customer	Power Savings	Techniques/Methodology	Application
KeyStream	50%	RTL architecture trade-offs RTL power visibility Clock Wattbots	802.11a/b/g wireless LAN chipsets
Ubicom	25%	Clock Wattbots (RTL power within 5% of gates)	Communications and Media Processor
Tensilica	25%	Clock Wattbots Power regressions	Configurable and standard microprocessor cores
Video IP Company	30%	RTL power visibility - work on modules consuming highest power Clock power reduction Power-efficient memory Power vectors for all modes (RTL power within 10% of gates)	Multi-core DSPs for IP network surveillance, video conferencing, etc

To achieve their low-power targets, SoC designers must take a top-down approach beginning at the architectural level, continuing through RTL analysis and through power sign off. Applying these techniques early and often, using PowerTheater, can reduce power 30-50%.

As part of the Sequence Design For Power flow, we are working with low power standards initiatives including the Si2 Low Power Coalition (LPC) Common Power Format (CPF) and the Unified Power Format (UPF) to enable low-power intent through implementation tools once micro-architectural trade-offs and power sign off is done at the RT level.

As power management challenges continue to grow, we will continue to work in partnership with our customers to provide the tools and techniques necessary to address power early in the flow. This offers the chance to maximize power savings early where the most can be gained, and also puts low power design top of mind, so it can be incorporated at every step along the way.