Both of them deal with a vitally important subject - current efforts to establish a single standard format for including power-aware design, verification and implementation details in EDA design flows. I believe we are converging on this standard through the ongoing work of the industry committees, and am pleased to help promote this concept by participating in these informative panel discussions. Hope to see you there!

As is usually the case, we expect a packed house for our DAC Demo Suites, so I encourage you to register early. You can get more information and register online at: www.sequencedesign.com. We will also be e-mailing most of you with additional details, so be sure to plan spending some time with Sequence while in sunny San Diego.

It has been a great year for us. We have long preached the necessity of making designs "power-aware" from beginning to end of the flow, and it seems to be paying off as the company experienced 18% bookings growth in 2006, and is currently serving more than 150 customers worldwide.

Since DAC 2006, we have achieved significant technology breakthroughs, and incorporated them into our all-star product lineup. PowerTheater 65, for example, addresses the complex issues of low-power design at 65nm and below, and is the industry's first RTL power analysis and management solution with physical-design features to insure results that closely relate to real silicon. PowerTheater 65 has enhanced its singular ability to accurately estimate power at RTL with a host of new silicon-aware features for voltage islands, mixed Vt, power gating, and clock gating.

PowerTheater 65's early visibility into design tradeoffs at RTL has proven invaluable for competitive specs, cost, yield, and reliability, among other benefits. We have also added enhanced clock power estimation and reduction, since clocks often consume 30% to 50% of total chip power. Customers, such as communications and media processor standout Ubicom, are typically reducing power 25% or more thanks to these enhanced capabilities.

CoolTime and CoolPower, the industry's leading low-power physical analysis and optimization tools, added breakthrough SMMART (Sequence Macro Modeling using Advanced Region Technique) technology for advanced modeling of memories and other macros for SoC dynamic voltage-drop analysis. SMMART provides highly accurate representations of macros for chip-level analysis, with no capacity limitations. Our good friends at Genesis Microchip reported that CoolTime improved throughput and memory usage by 30 percent respectively.

The Columbus extraction product family has also experienced significant improvement with Speedview-AMS, enabling fast, efficient diagnosis of EM and V-drop issues in full-custom designs; and statistically accurate PVT corner extraction, along with new features to enable a best-of-breed flow for extracting and analyzing power rails in full-custom blocks using Columbus-AMS.

In 2006, Sequence was awarded its 22nd patent, and continues to invest in R&D activities at our global "Centers of Excellence" to remain a step ahead of the competition. Our 2007 focus is on strengthening the Sequence product lineup to deal with the increasingly difficult challenges designers are facing. We are actively working with customers and partners to establish a complete "ecosystem" for power-aware design success at 65nm and 45nm, and will soon unveil a range of features that make our tools more silicon-aware, and provide high-level insights into power management.

Naturally, we'll have much more to tell you at DAC, particularly how a range of new features promises to make low-power design faster, better, and more intuitive. My goals for the coming year: Delight the customer! Continue creating excellent products! And have fun! Look forward to seeing you soon and to sharing our success journey together. Best wishes, Vic.