Great seeing so many of you at DAC! Talking with customers and colleagues there, it is clear that power remains a major focus for designs below 90nm. So it was very gratifying to see the enthusiastic response to Sequence's "Design For Power" (DFP) initiative we rolled out at the show.

DFP represents a holistic approach to power, enabling power exploration from the architectural level through physical implementation, reducing power while preventing power problems in timing, SI, and power grid design, with our unique silicon-aware design techniques. Customers already employing Sequence's DFP Flow are reporting RTL power reduction of up to 50 percent, a 50 percent speedup in design closure times, and leakage power reduction of up to 1,000X.

The DFP Flow comprises PowerTheater for RTL power analysis and reduction, with new PowerTheater-Explorer for power visualization and debug. Accelerated design closure, power reduction, and power-grid integrity is supplied by the company's CoolProducts family, now with power gating analysis and simultaneous switching noise options. The award-winning Columbus extraction engine provides statistical corner parasitics for significantly increased margin in the DFP flow.

We have posted a demo on the home page that describes this exciting technology in depth which I encourage you to check out, or contact us directly for more information.

Moving forward, we recognize that DFP goes beyond tools, so we are very active with industry colleagues and organizations to promote a design "ecosystem" since no one company can provide all the answers. A good example is our collaborative efforts with ESL vendors such as Bluespec, CoWare, Forte, NEC Cyber, Mentor and Synfora. The importance of these relationships was summed up by Mentor's Shawn McCloud, product line director for high-level synthesis.

"To a large degree, ESL design is driven by the power-sensitive portable electronics market. ESL methodologies move critical design decisions to earlier in the design process, giving designers more freedom to make architectural changes that can have the greatest impact on power consumption. The Mentor/Sequence combination delivers an automated power exploration flow that helps designers reduce power consumption by as much as 30% for their next-generation portable applications."

As many of you know, Sequence has also been heavily involved in promoting common industry power standards, and continuously getting customer feedback on the importance of reaching consensus. We recognize that design success is increasingly dependent on multiple-tool flows, and that interoperability should be a given in a customer-driven business like EDA. So I am happy to report that we are making great progress in converging on a single low-power standard - after all, we have gone from some 20 proposals to just two today, so we are very close!

Another important issue on the Sequence radar, and one that received a great deal of attention in the past year is Design For Manufacturing (DFM). Process variation is a real issue that can have dire consequences for yield and silicon success. Today our customers recognize the importance of accurate extraction provided by the Sequence Columbus family of products to head off the effects of process variation by moving these issues up in the design flow - particularly important at 65nm and below. Look for a success-story announcement from a major Japanese customer on this topic in the near future.

In closing, I would like to take a moment to thank Richard Goering for his long career at EE Times. He was a champion of new technologies and excelled at taking difficult concepts and communicating them to his readers in illuminating ways. We wish him well, and look forward to working with him again soon.