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 Low
power industry panel co-sponsored by Cadence and the India Semiconductor
Association (ISA) |
| Accelerating
Low Power Design: The New Industry Imperative |
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Bangalore,
India
Dec. 12, 2006
Moderator: Local media editor
– Name, TBD |
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Panelists |
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| Cadence: |
| Chi-Ping Hsu: The Common Power
Format: Automating low-power design
Chi-Ping Hsu is Corporate Vice President, Chief strategist,
Products and Technologies. Before that he was Corporate Vice
President of synthesis solutions and Power Forward Initiative.
He was President and COO of Get2Chip before merging with Cadence
Design systems in April 2003. Prior to Get2Chip, Hsu was CTO
at Avant! for seven years, where he played a crucial role
in the growth of the Avant! annual business from $7M to $380M.
He led the engineering, product strategies, marketing, business
development, M&A, and strategic investments. His vision,
management, and execution led to the success of Avant! in
the marketplace from 1995 to 2001. Prior to Avant!, Hsu held
senior management positions in both engineering and marketing
at Hughes, Cadence, and Pie/Quickturn. He has made significant
impacts on the industry by delivering key market-leading EDA
products. He holds a Ph.D. degree in EECS from University
of California, Berkeley, and BsEE degree from National Taiwan
University.
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| TSMC: |
Ashwin Ramachandran: Accelerating
low power design using the Common power format
TSMC Country Manager |
| Sequence: |
| Koushik Roy: Integrating power
throughout design flow |
| Koushik Roy is the Director
of Sequence Design’s India R&D Operations, has been
working with Sequence Design since March, 2006. He is responsible
for the product development activities in Sequence Design India.
He has over 21 years of industry experience. Prior to Sequence,
he has worked in Synopsys and Cadence where he was responsible
for the development, management and delivery of critical technologies
& tools like PSL (VCS), Assertion Based Verification(NCSIM),
Analog Mixed Signal(NCSIM), System Verilog(NCSIM), NC-SystemC
and NCVHDL.
Having worked in India and USA, Koushik has expertise in
global, multi-cultural team management and product development.
He worked in Uptron Digital Systems where he had hardware
design experience. Koushik has been contributing to standards
organization like Accellera and Si2. He is an alumni of Jadavpur
University, Calcutta where he received his BE in EE and ME
in CSE. |
| ARM: |
Rahoul Varma: Advanced power
lowering techniques
Manager - PDCI Bangalore ARM Embedded Technologies Pvt. Ltd.
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| Freescale: |
Milind Padhye: Low power design
requirements
Low Power Design Manager |
| Milind Padhye is Low Power
Design Manager at Freescale Semiconductor, Wireless design organization
in Austin Tx. He has been working in the field of low power
design for last five years and has multiple patents and disclosures
filed for power reduction techniques and integration. He has
lead multiple chips for low power architecture and design. Prior
to Freescale, Milind worked for Motorola India design center
and lead multiple Soc products and tapeouts. |
| Abstract: |
| There is no question that
low-power design has become a primary concern for IC design.
It affects all systems, not just battery-operated portable types.
From IC packaging, to enclosure sizes, to cooling methods, lower-power-consuming
ICs are on every system designer’s wish list. As for the
IC design process itself, several advanced techniques have emerged
to lower power in SoCs including multiple supply voltages, dynamic
and adaptive voltage-frequency scaling, and power shut off.
However, these new techniques challenge existing tools and methodologies.
Fortunately, new approaches have surfaced to help manage and
maintain power-related information through the design flow.
In this forum, the panelists present real life design scenarios
and successes achieved using these new techniques and will highlight
future requirements. |
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