:: Sequence Design :: Press Releases on Low Power Design,Power Integrity,Signal Integrity,Timing Analysis,Leakage Power,SoC Design,Dynamic Voltage Drop,Power Gating

Sequence Design - In The News

INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2008"
deepchip.com

Sequence PowerArtist Identifies Ways to Reduce Power
icjournal.com

BWhat to see @ DAC 2008
garysmitheda.com

Buzz@DAC & Kuhl@CAL
edacafe.com
May, 2008

45th DAC Takes The SoC Methodology Plunge
electronicdesign.com
May 22, 2008

techon.nikkeibp.co.jp
May 20, 2008

Ten-Step Program
icjournal.com
May, 2008

Sequence PowerArtist promises fast RTL power reduction
scdsource.com
May 19, 2008

Design for low power: Sequence offers to automate what the experts do by hand
edn.com
May 19, 2008

Think Globally, Excel Locally
siliconindia.com

Among Design Constraints, Power Assumes The Throne
electronicdesign.com
January 22, 2008

Tame the Timing Margins in Your 65-nm Designs
soccentral.com
January 03, 2008

Understanding RTL power reduction techniques
scdsource.com
December 05, 2007

Coverage of Sequence Design for Power (DFP) Seminar 2007 held in Tokyo
china.nikkeibp.co.jp
November 21, 2007

Coverage of Sequence Design for Power (DFP) Seminar 2007 held in Tokyo
techon.nikkeibp.co.jp
November 15, 2007

Stanch The Bleeding Of Leakage Power At 65 nm
Electronic Design
November 05, 2007

Sequence Extends Low-Power Leadership: Two New Patents, CTO Frenkil Featured In New Design Tome
Yahoo Finance
November 02, 2007

Stream Processors Selects Sequence PowerTheater for Optimization
chipdesignmag.com
October 17, 2007

Interview of the Week at EPN Online: With Vic Kulkarni
epn-online.com
October 15, 2007

Perform Design-for-Test and Power Management at the RTL
chipdesignmag.com
September, 2007

Minimera effekt-förbrukningen tidigt
ELEKTRONIK I NORDEN (Sweden)

India: On the road to superpower
SiliconIndia Magazine

EDN Japan Sept 2007

Power Forward Initiative Newsletter
cadence.com

PowerTheater in Toshiba flow
toshiba.com

Power Management Poses a Critical Design Constraint in the SoC World of Consumer Applications
SoCWorld.Toshiba.com

Perform Design-for-Test and Power Management at the RTL
chipdesignmag.com
September, 2007

Sequence 2nd Annual Design for Power (DFP) Seminar
businesswireindia.com
September 06, 2007

Automating the SSN verification challenge
edatechforum.com
September, 2007

Cooley Does DAC
deepchip.com

Analyzing dynamic voltage drop at 90 nm and beyond
EE Times
August 06, 2007

Faraday Technology Enhances PowerSmart(TM) Design Flow to Include Sequence's RTL Power Analysis Tool
news.thomasnet.com
July 17, 2007

Sequence CoolProducts Chosen by Tektronix for Power Signoff
SOC central
July 10, 2007

Sequence CoolProducts Chosen by Tektronix for Power Signoff
Yahoo Finance
July 10, 2007

anything you can do...
powerforward.org
July, 2007

PowerTheater Accuracy
ELECTRONICS MAGAZINE (ISRAEL)

How TenSilica uses Sequence's PowerTheater tool
deepchip.com
June 28, 2007

Commentary: Determining the cost of power
eetimes.com
June 15, 2007

STARC Adding Sequence Power-Gating Analysis to Advanced Design Flow
EDACafe.com
June 04, 2007

ELETTRONICA OGGI MAGAZINE (ITALY)
June, 2007

Sequence Upgrades Columbus Parasitic Extraction
SOC central
May 29, 2007

Sequence Columbus Discovers New World of Performance
Yahoo Finance
May 29, 2007

Sequence and Mentor Graphics Collaborate on ESL Power Exploration Flow
Yahoo Finance
May 24, 2007

Don't Forget the Little Guys (at DAC)
SOCcentral
May 23, 2007

eda-express.com
May 23, 2007

Power-Analysis Engine Adds Visualization And Debug
Electronic Design
May 21, 2007

techon.nikkeibp.co.jp
May 21, 2007

techon.nikkeibp.co.jp
May 17, 2007

Sequence Debuts PowerTheater-Explorer for Power Visualization, Debug
edageek.com
May 16, 2007

eda-express.com
May 14, 2007

SANYO Semiconductor Signs Sequence's Columbus-AMS for Fast, Accurate Mixed-Signal Designs
EDACafe.com
May 14, 2007

DAC Preview: Front-End Design
Electronic Design
May 08, 2007

Low-power IC design techniques may perturb the entire flow
eetimes.com
May 07, 2007

Breakthrough in Setting Optimum System LSI Chips' Design Margins for the 65-nanometer Node and Beyond
necel.com

Key Stream Hits Low-Power Goals with Sequence's PowerTheater
Yahoo Finance
April 23, 2007

necst.co.jp
April 23, 2007

Top-down analysis critical for power-aware design success
eetindia.com
April, 2007

The same but different
cieonline.co.uk
April, 2007

NEC System Technologies Interfaces CyberWorkBench ESL Synthesis Tool with PowerTheater
soccentral.com
April 16, 2007

Lower power becomes bigger issue
EDN.com
April 06, 2007

ESNUG: We got 2X design at less power with PowerTheater - Jack Choquette, Azul Systems
deepchip.com
March 30, 2007

ESNUG: Answers from Vic Kulkarni, CEO of Sequence
deepchip.com
March 16, 2007

EDA in India
EDACafe.com

Stretch Turns to Sequence CoolTime and CoolCheck
SOC central
March 06, 2007

eettaiwan.com
March 05, 2007

Macro Models Serve Dynamic Voltage-Drop Analysis For SoCs
Electronic Design
March 01, 2007

Low-power design solutions
The Machinist
February, 2007

Sparks fly at EDA 'troublemakers' panel
EE Times
February 23, 2007

'Statistically accurate' PVT corner extraction rolls
EE Times, Asia
February 16, 2007

Be Early with Power
chipdesignmag.com

Sequence Columbus-AMS Adds Statistically Accurate PVT Corners, Superior Rail Analysis
soccentral.com
February 13, 2007

EDN Japan

La Verifica Formale Al Servizio Dell'alimentazione
Technologie SoS

Design & verification conference & exhibition
dvcon.com

eda-express.com

Macro modeling supports voltage drop analysis
eetimes.com
February 6, 2007

Sequence Tackles Silicon Failures with SMMART Macro Modeling for Dynamic Voltage Drop Analysis
soccentral.com
February 6, 2007

Vic Kulkarni Details Sequence's Low-Power Success Formula in SiliconIndia Cover Story
Yahoo Finance
February 5, 2007

Sequence Design to focus on low power consumption chips
thehindubusinessline.com
February 5, 2007

Sequence Design: Enabling energy efficient SoC design
SiliconIndia Magazine

ESL Synthesis + Power Analysis = Optimal Micro-Architecture
chipdesignmag.com

Breakthrough in Setting Optimum System LSI Chips' Design Margins for the 65-nanometer Node and Beyond
NEC Electronics
January 31, 2007

Bandspeed Optimizes Packaging, Power with Sequence's PowerTheater
soccentral.com
January 30, 2007

Analyseur des bus d'alimentation
Electronique International
January 22, 2007

Gain Abstraction And Accuracy From RTL Power Estimation
Electronic Design
January 18, 2007

Parser supports Cadence IC power standard
EE Times
January 17, 2007

Cadence releases Common Power Format source code
EDN
January 17, 2007

Si2’s Low Power Coalition Issues Request for Technology
Business Wire
January 12, 2007

Down Come The Walls Between Software And Hardware Design
Electronic design
January 11, 2007

Sequence Delivers DVD-Aware Timing, Advanced Power Flow for Sandbridge Technologies Next-Gen Wireless Designs
Yahoo Finance
January 11, 2007

Sequence Bringing All-Star, Power-Aware EDA Lineup to Japan’s EDSF
Business Wire
January 08, 2007

EDA '07 forecast: strong, but watch the bumps
EE Times
January 02, 2007

Sequence Highlights Low-Power Design at India’s VLSI Design Conference
Business Wire
December 27, 2006

techon.nikkeibp.co.jp
December 17, 2006

User Name: sequencedesign
Password: santaclara

techon.nikkeibp.co.jp
December 10, 2006

User Name: sequencedesign
Password: santaclara

Power Exploration in High-Level Synthesis
fpgajournal.com
December 19, 2006

India Semiconductor Association highlights the importance of low power design as a critical driver for the electronics industry
indiaprwire.com
December 15, 2006

Cool Products review on John Cooley's Deepchip!
deepchip.com
December 14, 2006

Ubicom Demonstrates 25% Power Reduction With Sequence PowerTheater
Yahoo Finance
December 12, 2006

Sequence Welcomes Pextra Corporation As Newest In-Sequence Partner
Business Wire
December 05, 2006

EDA Express
December 01, 2006

NEC Electronics
December 01, 2006

Columbus In Use at NEC
NIKKEI NET
December 01, 2006

Sequence revs clock power with PowerTheater 65
EE Times
November 20, 2006

Commentary: One IC power standard, please!
By: Vic Kulkarni
EE Times
November 17, 2006

EDAC panel to probe business in India
By: Richard Goering
EE Times
November 17, 2006

Sequence Wins Top si100 Spot Two Years Running
dbusinessnews.com
November 15, 2006

PowerTheater 65 improves clock power, Sequence says
By: Dylan McGrath
EE Times
November 14, 2006

EDA Consortium Co-Sponsors a Panel - 'How to Do Business in India' - November 28, 2006
Yahoo Finance
November 14, 2006

Ausdia First Services Company To Join Sequence Design’s In-Sequence Program
Business Wire
November 13, 2006

Low Power Raises the Heat
Business Wire
November 10, 2006

Sequence Wins Top si100 Spot Two Years Running
EDACafe.com
November 08, 2006

Sequence Wins Top si100 Spot Two Years Running
Yahoo Finance
November 08, 2006

Sequence Continues Tradition Of Innovation With 22nd Patent
Business Wire
November 06, 2006

Sequence, Synfora team on SoC power, architecture
EE Times
November 01, 2006

Cadence and Si2 Collaboration Paves the Way to a Unified Low-Power Standard
Yahoo Finance
November 01, 2006

Sequence Teams With Synfora to Optimize SoC Power and Architecture
EDACafe.com
October 30, 2006

Power standard standoff reaches stalemate
By: Richard Goering
EE Times, Asia
October 16, 2006

D. Lin, H. Stump: "RTL-Leistungsanalyse und -optimierung"
www.EuE24.net - Das Knowledge Portal für Elektronik & Entwicklung

Cool Products review on John Cooley's Deepchip!
deepchip.com
October 5, 2006

Sequence CEO Vic Kulkarni offers Thoughts on Globalization of Tech Biz in Major Interview
Business Wire India
October 4, 2006

RTL-Leistungsanalyse und-optimierung
E&E-Kompendium

EDA rivals spar over power issues
EE Times
September 18, 2006

The Age of Enlightenment. A Conversation with Vic Kulkarni …
By: Peggy Aycinena
September 18-22, 2006
EDACafe.com

Sequence Low-Power Presentation Highlights SAME 2006; Talk Describes Novel Method To Reduce Power-Switch Size Nearly 90%
Business Wire
September 19, 2006

Chip designers work to tame electromigration
EE Times
September 18, 2006

Survey finds designers concerned about power
EE Times
September 14, 2006

Accellera considers power format standards effort
EE Times
September 6, 2006

Sequence Sponsoring MemCon Sept. 12-14
Yahoo Finance
September 6, 2006

Power Forward Initiative Broadens Industry Support, Accelerates Standardization of Common Power Format
MARKET WIRE
September 5, 2006

Power Forward Initiative Speeds Format Standardization
By: Ann Steffora Mutschler
Electronic News
September 5, 2006

Cadence moves to broaden power initiative
By: Richard Goering
EE Times
September 5, 2006

Sequence Wows Bangalore Designers At Low-Power Seminar
Business Wire
September 1, 2006

World's Largest Semiconductor Memory Conference Highlights Leading-Edge Memory and Storage Solutions
Design and Reuse
September 1, 2006

Sequence CTO Jerry Frenkil To Speak At 4th Annual International SoC Conference
Business Wire
August 31, 2006

Sequence CTO Jerry Frenkil To Speak At 4th Annual International SoC Conference
Yahoo Finance
August 31, 2006

EDA tool finds uncovered electromigration issues
By: Dylan McGrath
EE Times
August 30, 2006

Columbus-AMS Announcement
EE Times: Print Edition
August 28, 2006

Power rails get analysis at Sequence
By: Dylan McGrath
EE Times
August 28, 2006

Rival efforts tackle low-power standards
By: Richard Goering
EE Times
August 07, 2006

Sequence Brings Power-Aware Lineup To Taiwan's EDA&T Aug. 17-18
EDAcafè
August 03, 2006

Roundup: EDA design tools
By: Jim Harrison
Electronic Products

Design Automation Conference presents latest design tools
By: Jim Harrison
Electronic Products

Sequence in Japan eda-express
July, 2006

Startup Athena tops Cooley's DAC 'must see' list
By: Dylan McGrath
EE Times
July 21, 2006

Sequence Clock Power, Voltage Island Analysis Bests Competition
Yahoo Finance
July 19, 2006

Sequence Clock Power, Voltage Island Analysis Bests Competition;
Simplifies Tricky Analysis and Optimization While Chopping Up To 40% Off Power Budget
CEN
July 19, 2006

Group formed to advance Liberty modeling standard
EE Times - India
July 18, 2006

'Silicon aware' tool tackles power at RTL
EE Times: Design News
July 17, 2006

Sequence's Silicon Aware PowerTheater 65 Tackles Power Early At RTL -- Adds Mixed Voltage Capabilities
Yahoo Finance
July 17, 2006

10 join Liberty tech advisory board
EE Times: Design News
July 16, 2006

Liberty Standard Technical Advisory Board Formed
EFY News Network
July 14, 2006

Semiconductor and IP Industry Leaders Join Synopsys and Si2 to Advance Liberty Modeling Standard
Yahoo Finance
July 13, 2006

Virage Logic's DAC Program Features Integrated Design Solutions for Accelerating Silicon Success;
IP Industry Leader Showcases VIP Partners, Business and Technical Sessions at DAC
Business Wire
July 13, 2006

DAC Preview: Physical Design And Analysis
Electronic design
July 11, 2006

Startups integrate ESL synthesis, power estimation
EE Times: Design News
July 06, 2006

Sequence Low-Power Design Seminar Coming to Bangalore on August 30th
Hindustan Times
July 03, 2006

ESL, Power, Interconnect, and DFM (Oh My!)
By: Clive (Max) Maxfield, Design Automation Conference
June 08, 2006

Der rechte Strom am rechten Ort PDF
Design & Elektronic
May, 2006

Sequence Boosts Usability, Performance Of Power-Grid Integrity Solution
EDAcafè
April 27, 2006

Sequence offers enhanced power-grid verification products
EE Times
April 27, 2006

Sequence expects to turn profit
EE Times
April 21, 2006

Sequence, Arithmatica Partner to Advance SoC Low-Power Design
NE Asia Online
April 18, 2006

Sequence, Arithmatica partner on SoC design
EE Times
April 11, 2006

Sequence Expands India Operations
EFYTimes
April 03, 2006

Green, Green, is Green they say ...
EDA Confidential
March 22, 2006

Sequence Goes Green For St. Patty's Day
EDAcafè
March 17, 2006

Sequence and DavanTech Sponsor Low-Power Design Seminar in Seoul
Embedded Star
March 17, 2006

Sequence White Paper: A Concurrent Method for Voltage-Drop Analysis and Optimization
TechOnLine
March 16, 2006

Japan's STARC Certifies Sequence's PowerTheater and CoolTime For Low-Power, High-Performance Production Flow
SOC Central
March 10, 2006

Sequence addresses needs of SoC designs below 90nm
EET Asia
March 07, 2006

Power analysis tool suite adds SystemVerilog support
EE Times
February 28, 2006

Sequence revamps Columbus-AMS
EE Times
February 23, 2006

Focus on Power at Japan ESDF: Sequence Design
Tech-On! Nikkei Electronics
February 21, 2006

Your Power Grid Isn't Good Enough
SOC Central
February 20, 2006

Sequence Chosen By Genesis Microchip For Voltage Drop and Power-Grid Integrity
Yahoo Finance
February 07, 2006

Holly Stump Joins Sequence as VP Marketing
Yahoo Finance
January 31, 2006

Featured Audio Interview - Vic Kulkarni, President & CEO, Sequence Design, Inc.
EDAcafè
January 30, 2006

Bullish on India
EE Times India
January 23, 2006

Sequence Low-Power Design Tools to Highlight Japan's EDSF
EDAcafè
January 11, 2006

Sequence partners with Korean foundry on power-aware flow
EE Times
January 03, 2006

EDA execs: ESL, DFM will stand out in lackluster '06
EE Times
January 02, 2006

Asia takes up systems design for consumer applications
EE Times India
January 01, 2006