 Power-Aware
Design Flow Seminar for 130nm to 65nm SoCs |
Is Power an Issue in your SoC Design?
Power-Aware Design Flow Seminar for 130nm to 65nm SoCs
September 14, 2006
Two Opportunities
Morning Session: 9AM - 12noon
Complimentary Lunch: Noon (both sessions)
Afternoon Session: 1PM - 4PM
Marriott San Diego La Jolla
4240 La Jolla Village Dr,
La Jolla, CA 92037
858-587-1414
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| This half-day seminar on SoC
power issues, solutions and analysis techniques is brought to
you by Sequence Design, the leader in low power
design , and Arithmatica, the silicon math
company. |
- Review components of power consumption
in ASIC designs.
- Determine Power Design pitfalls and
techniques to resolve
- Learn new power issues in 90 nm and
65 nm design flows
- Learn of datapath synthesis tool
that will optimize area, delay and power.
- Quickly learn how to effectively
use PowerTheater with optimum accuracy and performance.
- Clock Trees & High Fanout
Nets
- Power Gating
- Vector Analysis and Refinement
- Mode Power
- Multi-Voltage Designs
- Understand the Power Management
methodology for HDL based design flows.
- Learn about new tools available
to achieve your power goals and save you time
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| Don't miss this opportunity
to determine how to implement power saving design techniques
and implement tools that will help you reach your power goal
in half the time of your current tools. |
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