David Maliniak
ED Online ID #3038
March 3, 2003

Voltage-drop effects across an SoC weave a tangled web that impacts design closure. The key to unraveling it is instantaneous, dynamic voltage-drop analysis. One of the most pressing challenges of SoC design is power-grid design and analysis. At geometries of 130 nm and smaller, the effects of supply voltage drops go well beyond false logic transitions and thermal issues. Voltage drops across the die have pernicious physical effects on timing, coupling delays, and noise.

Voltage drops obviously become even more critical as supply voltages fall to 1 V dc and below. A 100-mV drop from a 2.5-V supply isn't necessarily an issue. But for a 1-V supply, it's 10%. That's a benchmark figure for many SoC designers who try to limit their worst-case drop, anywhere on the die, to 10%. Traditionally, the approach assumes an ideal uniform voltage, figures on a 10% safety margin, then calculates timing, delay, and noise within that envelope. But the realities of nanometer design have made this approach untenable.

Accurate analysis of voltage drops and attendant electromigration issues depend on accurate power analysis as well as parasitic extraction. Existing EDA tools provide analysis for one or more of these effects, but a concurrent approach is missing. In its CoolTime design platform, Sequence Design offers a tool that analyzes nanometer effects in parallel.

Existing voltage-drop analysis methodologies take a purely static approach to a dynamic problem. In the real world, current consumption and voltage drops vary over time. Static approximations fail to account for capacitive and inductive effects on the power grid and package, and both are dynamic in nature. When used with Sequence's static-timing-analysis (STA) technology, CoolTime yields an instantaneous voltage-drop analysis capability. It permits a concurrent assessment of the impact of voltage drop on timing, coupling delay, and noise.

Voltage drops affect logic-path timing in ways one might not anticipate (Fig. 1). If a gate at a higher supply voltage is driving one seeing a lower supply voltage, the rising edge will be faster but the falling edge slower than if both were seeing the same voltage. Failure to account for these voltage-induced timing violations can result in an unnecessary design turn. Such situations also degrade the noise margin for glitches.

The CoolTime approach to instantaneous voltage-drop analysis represents a synthesis of several Sequence foundation technologies. It incorporates the RLC extraction technology from Sequence's Columbus tool as well as the average-power analysis capabilities of its PowerTheater tool.

Today's voltage-drop analysis methods provide unpredictable results. After designing the power grid for their SoC, designers use a static IR-drop tool in a successive refinement process until they have less than a 5% IR drop on both their power and ground rails. Then they'll sign off on the grid and move to implementation. They'll use a library characterized for a lower voltage and assume that gives them enough of a margin to cover worst-case scenarios.

"This is an overly optimistic approach," says Piyush Sancheti, CoolTime's product marketing manager. Static IR-drop analysis doesn't guarantee a worst-case voltage drop because it depends on average current.

On the other hand, such analyses ignore on-chip decoupling capacitance between the power and ground rails. "This is the pessimistic side of the equation," says Sancheti. Timing and signal integrity end up being analyzed separately. Also, the guardbanding imposed by the assumptions implied in the library selections mean sacrificing performance.

In contrast, Sequence's methodology for power-grid analysis provides predictable results in a concurrent flow (Fig. 2). CoolTime uses STA techniques to compute switching events on all nodes. It then references the library energy models to compute instantaneous currents.

In the vectorless mode, CoolTime uses a patent-pending technique to precondition the design for a reasonable worst-case current consumption without the need for simulation vectors. Alternatively, CoolTime can be run using simulation activities as input. In this simulation-based instantaneous mode, the tool enables pruning simulation vectors to a small subset of interest. This pruned vector set is used to set the circuit state and node toggle information, which then computes the switching events.

CoolTime implements what Sequence has termed a fast IR-drop analysis mode to traverse a process of refinement (Fig. 2, again). Once major grid deficiencies are rectified, the user can move on to more fine-grained analysis to drive delay calculations for voltage drop, coupling, and crosstalk.

In addition, the tool analyzes both power and ground networks simultaneously to account for ground-bounce and resonance effects. It provides what the company calls a Voltage-Current Recorder, which generates a dynamic color map of current and voltage over time.

As inputs, the tool requires either hierarchical or flat Verilog, Design Exchange Format (DEF) files, or GDSII. Library inputs are in Synopsys .lib for power and timing and Library Exchange Format (LEF) for layout. Constraints are provided in Synopsys SDC format.

The static-timing and signal-integrity analysis results can be fed to Sequence's PhysicalStudio for performance optimization. The tool also outputs Standard Delay Format for node-by-node voltage-drop data as well as incremental and full coupling delays. Those outputs can be fed to the designer's sign-off timing-analysis tool of choice.

The tool is built for high performance. Instantaneous voltage-drop analysis runs at a rate of 400k placeable instances/hour, with one instance equal to four to five gates (2 Mgates/hour). Average/static IR drop analysis runs about 10 times faster. RLC extraction is performed at 3 million or more nets/hour in a multiprocessor environment. Capacity is rated at 1 million to 5 million placeable instances (5 to 25 Mgates).

U.S. list pricing for CoolTime starts at $150,000 for a one-year time-based license. It runs on Solaris 2.7-2.8 (32-bit) platforms with a maximum of 4 Gbytes of RAM. Beta tests are under way. General availability is scheduled for April.