CoolPowerTM* is the industry's leading cell-based Power Integrity solution for concurrent optimization of power, dynamic voltage drop, timing and signal integrity (SI) for nanometer SoC design. CoolPower predicts and corrects design closure issues both before and after routing. It gives users the ability to interactively optimize hierarchical, multimillion gate SoC designs at the block-level, as well as, full-chip level. CoolPower integrates into popular third-party place and route tools to enable existing physical flows to reach fast, predictable design closure in silicon geometries below 130 nanometers (nm).

• Achieves faster design speeds while maintaining longer battery life
• Complete power gating solution creates, optimizes, and verifies powergated designs

• Intelligent voltage drop optimization reduces leakage power and increases yield
• Automatically fixes dynamic voltage drop problems using decoupling capacitance insertion and peak power spreading techniques

• Reduces static leakage power and dynamic power
• Concurrent analysis preserves timing and signal integrity

• Pre-route creation and post-route repair reduces iterations
• Netlist and placement changes optimize timing, signal integrity, and voltage drop impact on timing

• Register-bounded methodology improves accuracy and increases capacity while reducing run-time
• Single-pass, push-down approach increases design performance and eliminates design iterations

• Integrated CoolTime concurrent analysis engine eliminates convergence problems
• Seamless integration with standard physical design flows and formats
• Easy-to-use graphical interface and detailed analysis reports