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Sequence
enables power-aware SoC design from system level to signoff.
Sequence has fortified its leadership in RTL power, dynamic
voltage drop and signal integrity closure with the unveiling
of exciting new solutions for power at Electronic System Level
(ESL) and concurrent physical optimization of leakage power
(MTCMOS power gating and multi- Vth), active power and dynamic
voltage drop. Sequence offers products for a system level
to signoff flow wherein power analysis and optimization are
seamlessly integrated at each stage in the user's existing
design and implementation flow. Sequence's unique solution
enables SoC designers to reduce time-to-market and chip costs
for power-aware applications. |
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Sequence Cool by Design Flow: Complementary to Cadence, Synopsys
and Magma |
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| PowerArtist™ is the industry’s
fastest automated RTL power reduction tool with a comprehensive
set of power reduction techniques targeting clock, memory and
datapath. With a powerful user-friendly cockpit and a wide range
of visual debug diagnostics, PowerArtist is the low power RTL
design tool. The RTL designer can quickly identify where power
is consumed, what it takes to reduce it, and control changes.
PowerArtist provides the flexibility to automatically rewrite
power-optimized RTL, output synthesis constraints, or guide
the user through manual RTL rewrites. With production-proven
RTL power analysis technology, the RTL designer can reliably
quantify power savings upfront. |
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| Power Theater™ is a comprehensive
set of power tools that help you create maximum power efficiency
for your SoC designs. Sequence is the only company delivering
power software focused at the architectural, RT and gate levels
of abstraction. Integration of PowerTheater with the leading
ESL design tools allows designers to explore alternate architectures
and optimize for performance, area and power requirements at
levels of abstraction higher than the RT level. In partnership
with ESL vendors enabling performance and area exploration,
Sequence takes the lead in tackling the power exploration problem. |
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| CoolTime™ is the industry's leading
cell-based electrical integrity solution for concurrent analysis
of voltage drop, power, electromigration (EM), timing and signal
integrity (SI) for nanometer SoC designs. Eliminating the need
for multiple point tools and iterations, CoolTime renders accurate
and convergent analysis of interdependent electrical effects.
CoolTime shares a common platform with CoolPower™ optimization
to ensure rapid design closure for dynamic voltage drop, leakage
power, EM, timing and SI effects. |
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CoolPower™
is the industry's leading cell-based Power Integrity solution
for concurrent optimization of power, dynamic voltage drop,
timing and signal integrity (SI) for nanometer SoC designs.
CoolPower predicts and corrects design closure issues both
before and after routing. It gives users the ability to interactively
optimize hierarchical, multi-million gate SoC designs at the
block-level as well as full-chip level. CoolPower integrates
into popular third-party place and route tools to enable existing
physical flows to reach fast, predictable design closure in
silicon geometries below 130 nanometers (nm). |
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| The Columbus™ product suite provides
unparalleled RLC parasitic extraction accuracy and versatility
to meet the design challenges at 90nm and beyond. Eliminate
costly re-spins and tape out your designs with confidence knowing
that interconnect parasitics won't compromise performance. Only
Columbus's patented extraction engine delivers the precision
needed to model on-chip variations in today's advanced process
technologies, allowing you to reduce guardbands and achieve
silicon success. Columbus offers both gate-level and device-level
extraction capabilities, ensuring integration into your power,
reliability and signal integrity flows for standard cell, custom
digital, mixed signal and analog designs. |
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Design For Power: Sequence Power-aware SoC Design Flow  |
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