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Power has emerged a key concern
for chip competitiveness and environmental considerations. It
is the early design decisions that largely determine the chip
power consumption. PowerArtist is the industry’s fastest
automated RTL power reduction tool working at RTL - the highest
level of hardware abstraction.
With a comprehensive set of techniques addressing clock, memory
and datapath, PowerArtist addresses the major power consuming
sections of the chip. Utilizing proven power analysis technology,
it increases designer productivity by quantifying power savings
upfront. The RTL designer can quickly identify where power is
being consumed, what it takes to reduce it, and control changes
through a powerful user-friendly graphical cockpit, PowerCanvas.
Depending on the reduction technique, PowerArtist can automatically
rewrite power-optimized RTL, output synthesis constraints, or
guide the user through manual RTL rewrite. The wide range of
visual debug diagnostics in PowerArtist significantly lower
the barrier for the RTL designer in creating low power RTL.
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 KEY
FEATURES & BENEFITS |
 Reduce
Power Early at RTL |
- Maximize power savings early with vectorless and vector-based
techniques
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| Comprehensive
Power Reduction |
- Clock: Reduce power beyond synthesis
with activity-smart additional clock gating
- Memory: Create power-efficient configuration
and control activity
- Datapath: Eliminate wasted power
- OpenAccess DB API: Automate proprietary
power techniques
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| PowerCanvas
Debug Cockpit |
- Graphically pinpoint and control powerordered reductions
- Easily debug power with a range of visual debug diagnostics
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| Proven
RTL Power Analysis |
- Rely on quantified power savings upfront before committing
RTL changes
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| Automated
Power Reduction |
- Enhance productivity with automated RTL rewrite
- Output synthesis constraints for clock gating
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| Performance
and Capacity |
- Run million gate-equivalent RTL in minutes with full-chip
capacity
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| COLLATERAL |
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