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PowerTheater
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Technical Papers
 
 Design Center Technical Articles
 Design For Power: VLSI / SOC Power Issues
Commentary: Determining the cost of power
eetimes.com
Low-power IC design techniques may perturb the entire flow
eetimes.com
Low Power Standards: The same but different
cieonline.co.uk
Lower power becomes bigger issue
EDN.com
Sequence Design: Enabling energy efficient SoC design
SiliconIndia Magazine
Survey finds designers concerned about power
EE Times
Low Power Raises the Heat
Business Wire
Managing Power in System-on-Chip Design
EDTN/ChipCenter
Tally Power into Cost of 'Free' Silicon
EETimes
A Multi-Level Approach to Low Power IC Design
IEEE Spectrum
 Design for Power: Front End
PowerTheater Accuracy
ELECTRONICS MAGAZINE (ISRAEL)
Top-down analysis critical for power-aware design success
eetindia.com
Low-power design solutions
The Machinist
Be Early with Power
chipdesignmag.com
ESL Synthesis + Power Analysis = Optimal Micro-Architecture
chipdesignmag.com
Gain Abstraction And Accuracy From RTL Power Estimation
Electronic Design
ESL, Power, Interconnect, and DFM (Oh My!)
By: Clive (Max) Maxfield, Design Automation Conference
Power Exploration in High-Level Synthesis
fpgajournal.com
D. Lin, H. Stump: "RTL-Leistungsanalyse und -optimierung"
www.EuE24.net - Das Knowledge Portal für Elektronik & Entwicklung
RTL-Leistungsanalyse und-optimierung
E&E-Kompendium
RTL techniques for optimizing power in SOC design
Computer Design
 Design for Power: Implementation
Automating the SSN verification challenge
edatechforum.com
Analyzing dynamic voltage drop at 90 nm and beyond
EE Times
ELETTRONICA OGGI MAGAZINE (ITALY)
La Verifica Formale Al Servizio Dell'alimentazione
Technologie SoS
Breakthrough in Setting Optimum System LSI Chips' Design Margins for the 65-nanometer Node and Beyond
NEC Electronics
Analyseur des bus d'alimentation
Electronique International

NEC Electronics
Chip designers work to tame electromigration
EE Times
Der rechte Strom am rechten Ort PDF
Design & Elektronic
Your Power Grid Isn't Good Enough
SOC Central
An Analysis Methodology for Dynamic Power Gating
By Ken Choi and Jerry Frenkil
Coping with 65nm Interconnect Variations using Statistically Accurate Corners
By Rob Mathews
 Cooley DeepChip Links on Power
Cooley Does DAC
How TenSilica uses Sequence's PowerTheater tool
ESNUG: We got 2X design at less power with PowerTheater - Jack Choquette, Azul Systems
Cool Products review on John Cooley's Deepchip!
 Whitepapers
 Leakage Power and PowerTheater
 A Concurrent Method for Voltage-Drop Analysis and Optimization
 Your Power Grid Isn't Good Enough (CoolCheck™)
 Instantaneous Voltage Drop Analysis in Sequence CoolTime™
 Impact Of Coupling On Interconnect Delays: Devil Is In The Modeling
 Modeling Skin Effect In Resistive Interconnect
 Is Inductance Becoming Critical For Deep Submicron Interconnect?
 The Effects of Very Deep Submicron (VDSM) Copper Processes
 Interconnect Parasitic RLC Effects on Performance of RF Designs
 
White papers are available for qualified prospects and customers of Sequence Design. Universities may also submit requests.
Sequence Design, Inc. reserves the right to not to provide this data to any individual or entity.
  IC Power Research Links
Electronic Design Process Subcommittee of IEEE DATC: EDP 2007 Workshop
  1. Words of Power: Reusable, Holistic, Scalable Multi-voltage Design
    Herve Menager, CTO SoCDT NXP
  2. "System level considerations/tradeoffs in the design of SoCs for portable video applications"
    >> download Paper
    Mahesh Mehendale, Texas Instruments
  3. Cutting across abstractions
    Krisztián Flautner, ARM, Inc.
  4. Power Management Design Challenges
    Milind Paddhye, Freescale, Inc
  5. EDA to the Rescue of the Silicon Roadmap
    Marco Casale-Rossi, Synopsys
  6. "Should Power Management Govern Design Hierarchy?"
    Ed Huizbregts, Magma Design
  7. "Power Management Early in the Design Flow: Exploration to Implementation"
    Holly Stump, Sequence Design
VLSI Design Automation Lab: University of Michigan
Stanford Ultra Low Power Group
 
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