CoolCircuit April '07

	SEQUENCE COOLTIME/COOLCHECK A HIT WITH STRETCH
	BANDSPEED OPTIMIZES PACKAGING, POWER WITH SEQUENCE'S POWERTHEATER
	SEQUENCE DELIVERS DVD-AWARE TIMING, ADVANCED POWER FLOW FOR SANDBRIDGE TECHNOLOGIES NEXT-GEN WIRELESS DESIGNS
	EDA IN INDIA
	MACRO MODELS SERVE DYNAMIC VOLTAGE-DROP ANALYSIS FOR SOCS
	LOW-POWER DESIGN SOLUTIONS
	BE EARLY WITH POWER
	SEQUENCE DESIGN: ENABLING ENERGY EFFICIENT SOC DESIGN
	ESL SYNTHESIS + POWER ANALYSIS = OPTIMAL MICRO-ARCHITECTURE
	GAIN ABSTRACTION AND ACCURACY FROM RTL POWER ESTIMATION
	SEQUENCE COLUMBUS-AMS ADDS STATISTICALLY ACCURATE PVT CORNERS, SUPERIOR RAIL ANALYSIS
	SEQUENCE PREVENTS SILICON FAILURES WITH SMMART MACRO MODELING FOR SOC DYNAMIC VOLTAGE DROP ANALYSIS
	DATE LOW POWER PANEL - APRIL 18, 2007\| ACROPOLIS, NICE, FRANCE, ROOM GALLIENI 4
	ELECTRONIC DESIGN PROCESSES (EDP) 2007 - APRIL 12& 13, 2007 \| MONTEREY BEACH HOTEL, MONTEREY, CALIFORNIA
	DVCON 2007 - THE TROUBLEMAKERS PANEL

See You At The Show! DATE and DAC are fast approaching, signaling a busy and rewarding time for all of us in EDA and the design community. It's a chance to share the latest and greatest technologies, catch up with old friends, and talk about that perennial topic of how to make EDA more than just the "raw material" in the electronic system value chain! I'll be on a pair of low-power panels at these shows:

DATE: Power-Forward Initiative Wednesday, April 18, 3:30pm Acropolis, room Gallieni 4 Registration: www.cadence.com/webforms/date2007/index.aspx		DAC: Low-Power Coalition Sunday, June 3, 12:30pm Registration: www.dac.com

Vic Kulkarni, President and CEO, Sequence Design

Both of them deal with a vitally important subject - current efforts to establish a single standard format for including power-aware design, verification and implementation details in EDA design flows. I believe we are converging on this standard through the ongoing work of the industry committees, and am pleased to help promote this concept by participating in these informative panel discussions. Hope to see you there!

As is usually the case, we expect a packed house for our DAC Demo Suites, so I encourage you to register early. You can get more information and register online at: www.sequencedesign.com. We will also be e-mailing most of you with additional details, so be sure to plan spending some time with Sequence while in sunny San Diego...More...

Sequence CoolTime/CoolCheck A Hit With Stretch

"Helps find issues early in the design flow . . .!"
Sequence Design's CoolTime and CoolCheck are winning praise from Stretch Inc., technology leader in software-configurable processors, for their valuable early-analysis physical design capabilities and ease of use...More...

Bandspeed Optimizes Packaging, Power With Sequence's PowerTheater

Sequence Design announced Bandspeed, a leading developer of mass-market Wi-Fi solutions, has chosen PowerTheater to reduce power in the next generation of Bandspeed's sophisticated 90nm AirMaestro SoC, thereby hitting aggressive power-management and package targets.
...More..

Sequence Delivers DVD-Aware Timing, Advanced Power Flow for Sandbridge Technologies Next-Gen Wireless Designs

Sequence Design, the EDA leader in power-aware SoC design solutions, announced that wireless IC pioneer Sandbridge Technologies has adopted Sequence's PowerTheater and CoolTime for "timing-aware" dynamic voltage drop optimization on its next-generation products...More...

ESNUG: Answers from Vic Kulkarni, CEO of Sequence

The real challenge is globalization. I believe in taking advantage of global trends, and am prepared to go wherever we have customers and wherever we can find talent...More...

EDA in India

It’s a simple enough question: Is there now, or will there be at some point going forward, an India-based EDA industry? The reason for asking the question seems obvious. The answer is not so obvious...More...

Macro Models Serve Dynamic Voltage-Drop Analysis For SoCs

Large macros and memories used in system-on-a-chip (SoC) designs can save time, but they can also be a bear when it comes to verifying them from a power-integrity standpoint...More...

Low-power design solutions

Those attending the sessions and walking the aisles of the VLSI show in Bangalore this year saw an overwhelming focus on the critical importance of low-power design...More...

Be Early with Power

The industry is undergoing a paradigm shift from getting a power number for their device to power management early in the design flow and throughout the design flow...More...

Sequence Design: Enabling energy efficient SoC design

For nearly two decades, the EDA industry has been missing the fundamental components of power management. Vic Kulkarni's team at Sequence Design is finding ways to tackle the perplexing puzzle...More...

ESL Synthesis + Power Analysis = Optimal Micro-Architecture

A new power-aware design methodology emphasizes the rapid, early exploration of different micro-architectures before locking onto a particular implementation...More...

Gain Abstraction And Accuracy From RTL Power Estimation

Excessive power consumption can destroy a design’s commercial viability. Modern cell phones are permitted to consume no more than a few hundred milliwatts for voice communications ...More...

Sequence Columbus-AMS Adds Statistically Accurate PVT Corners, Superior Rail Analysis

Sequence Design, the EDA leader in power-aware SoC design solutions, announced statistically accurate PVT corner extraction, along with new features to enable a best-of-breed flow for extracting and analyzing power rails in full-custom blocks using Columbus-AMS...More...

Sequence Prevents Silicon Failures With SMMART Macro Modeling For SoC Dynamic Voltage Drop Analysis

Sequence Design, EDA's power-aware SoC design technology leader, announced a range of new features for CoolTime and CoolPower, including breakthrough SMMART (Sequence Macro Modeling using Advanced Region Technique) technology for advanced modeling of memories and other macros for SoC dynamic voltage-drop analysis... More..

Industry Events Calendar
	Design Automation Conference - June 04-08, 2007 \| San Diego, California The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. Come see Sequence at Booth (you know the booth, you did the link) for the latest news and demos! Also, see Sequence on the Low Power Design Panel!...More...

	DATE Low Power Panel - April 18, 2007 \| Acropolis, Nice, France, room Gallieni 4 Type: Panel Date: Wednesday, April 18, 3:30pm - 4:30pm 2 The Power Forward Initiative was formed in May of 2006 with the primary goal to remove the barriers to automation of advanced low-power design techniques, and to provide a pathway to the development of an open standards-based solution for the industry... More...

	Electronic Design Processes (EDP) 2007 - April 12 & 13, 2007 \| Monterey Beach Hotel, Monterey, California The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves... More...

	TSMC Symposium: San Jose, Austin and Boston April 2007
	Sequence will participate in TSMC Symposium, "The Proven Path of Success," showing their complete low power design flow...More...

	DVCon 2007 - The Troublemakers Panel
	This year's "undignified" topics were: Magma's P&R market share, Vic promoting outsourcing to India, ClearShape's exit strategy, Cadence Tcl/SKILL/Pcell, Ciranova, Open Access, the Synopsys-Magma lawsuit, the Year of SystemC, small vs. large DFM vendors, Brion, the Mentor donut problem, Virtuoso 6.1, CPF vs. UPF, Sequence power tools, the Forte CEO exit, Forte vs. Bluespec, PrimeTime vs. Cadence ETS, the Infineon Magma 2 day timing closure letter, Magma Quartz vs. Mentor Calibre vs. Cadence PVS, worst EDA market stats, death of Dataquest, EDAC vs. Gary, price wars, and is EDA stagnating? Enjoy! ...More...

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's low power flow software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.

© Copyright 2007 Sequence Design, Inc. Cool by Design, CoolPower, CoolTime, PowerTheater, PhysicalStudio are trademarks of Sequence Design, Inc. All trademarks mentioned herein are the property of their respective owners.
Sequence Design, Inc. | 469 El Camino Real | Santa Clara CA 95050

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