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| As
we look back on a great 2006, I want to be sure to thank our
many customers, partners, and the entire Sequence team who
helped make this such a successful and rewarding year.
I am eager to carry this momentum into 2007 and beyond, and
am buoyed by optimistic reports from the SIA and others predicting
double-digit growth in semiconductor sales over the next few
years. One of the factors I believe will contribute to this
progress are emerging standards for common power formats that
have broad industry support, and promise to ease interoperability
and power-aware design.
On the technology front, we have made tremendous strides this
year across all product lines, and I am particularly proud
that we have received our 22nd patent for another breakthrough
in low-power design. PowerTheater 65 has been upgraded with
a host of new features specific to the challenges inherent
in designs at 65nm and below. Our CoolProducts now enable
much finer analysis and optimization for power-hungry items
such as clock trees, and offer support for the most advanced
power-aware techniques, including voltage islands. We also
continue to lead the way in extraction technologies with Columbus,
enhanced with a range of user-friendly features. |
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It has also been a terrific year for relationships with our
customers and partners. We have set attendance records at
a number of low-power design seminars held around the world,
thanks in large part to our corporate co-sponsors Cadence,
HP, and NEC, as well as the invaluable support of local distributors,
such as D'Gipro. We also had the pleasure of adding new members
to our In-Sequence family, promoting EDA interoperability
and advanced design methodologies, including our first design-services
partner, Ausdia, Arithmatica, Bluespec and Synfora. We capped
the year with the remarkable announcement of a 240X reduction
in leakage power achieved through advanced research with one
of our foundry partners, Dongbu Electronics.
Well, nostalgia is nice, but we are a forward-looking industry.
I believe next five years will require unprecedented levels
of cooperation among all industry segments in order to achieve
success at these incredible shrinking processes. For our part,
we will maintain our commit to, and leadership in, power-aware
design technologies as we have for the past decade. At the
same time, we welcome open standards and the chance to partner
with other innovative companies around the world to take on
any and all challenges the laws of physics may throw at us.
After all, success is a journey best enjoyed in the company
of friends!
Happy New Year, and may you enjoy continued happiness and
success in all things.
Vic Kulkarni
President and CEO
Sequence Design, Inc. |
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| Kishore Gottimukkala from GiQuilla
comments on CoolTime and Columbus in John Cooley's DeepChip! .. |
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| Communications and Media Processor
standout Ubicom has chosen Sequence Design's PowerTheater because
it demonstrated the ability to reduce power consumption in its multi-core
IC logic arrays by 25 percent. . |
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| Sequence Design, and Korea's Dongbu
Electronics Inc., one of the world's largest pure play wafer foundries,
announced test results demonstrating a 240X reduction in leakage power
using their jointly developed, advanced MTCMOS power-gating flow.
Power-gating design techniques significantly reduce leakage power
which can easily consume up to one-half of a modern SoC's power budget
if left unchecked.. |
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| John Cooley's Deepchip
site, source of fast breaking EDA news, presents an evaluation report
on Sequence's Cool Products. |
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Dr. Kimiyoshi Usami, a professor
at Tokyo's Shibaura Institute of Technology, and longtime member of
Sequence Design's Technical Advisory Board (TAB), presented a paper
on advanced power-gating techniques at the IEEE International Conference
on Computer Design (ICCD) in San Jose, Calif. |
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| Sequence Design has earned a coveted
spot on SiliconIndia’s annual si100 list for the second year
in a row. Honoring the top U.S. companies founded and managed by Indians,
the si100 award goes to those companies best exemplifying entrepreneurship,
innovation, and market leadership.. |
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| Formal grid verification provides
an early checkpoint in the design flow, during which a user can sign
off on the structural integrity of the power grid before proceeding
to voltage-drop and electromigration analysis. |
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| Excerpts of the conversation: Electronic
News sat down to discuss low-power design issues with Simon Bloch,
general manager for the design creation and synthesis division at
Mentor Graphics; Roger Carpenter, VP of strategic technology at Magma
Design Automation; Vic Kulkarni, president and CEO of Sequence; and
Shiv Tasker, president and CEO of Bluespec. |
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| Vic Kulkarni's EETimes Article:
I continue to be optimistic about current efforts to establish a single
standard format that will include power-aware design, verification
and implementation details in EDA design flows. It is the system-on-chip
(SoC) designers, our key constituency, who suffer when they are forced
to learn and maintain two different standards aimed at doing essentially
the same things. |
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| Pextra Corporation has joined Sequence
Design's In-Sequence Technology Partner Program, promoting EDA interoperability
and advanced design methodologies. Pextra, known for its IC and package
parasitic extraction acumen, is currently working with Sequence to
integrate its fast, accurate field solver technology with the Columbus
Library Builder. |
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| Ausdia has joined Sequence Design's
In-Sequence Technology Partner Program, promoting EDA interoperability
and advanced design methodologies. Ausdia specializes in helping clients
achieve rapid timing closure and chip convergence, and is the first
design services company to join the program. |
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| The creation of an integrated flow
incorporating Sequence's PowerTheater RTL power-analysis tool with
Synfora's PICO Express Application Engine Synthesis (AES). Strengthening
the collaboration, Synfora has joined the InSequence Technology Partner
Program, promoting EDA interoperability and advanced design methodologies.
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| Vic Kulkarni, president and CEO
of Sequence Design,in the featured interview in EDA Weekly, discussing
his long career, the impact of globalization on business, and how
Sequence is achieving success, particularly with its India R&D
operations. |
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| Area optimization and timing closure
have long been considered the most common digital design challenges
in mainstream digital IC design. Much has been analyzed and documented
on how to solve these issues at the various design levels –
from RTL to gate to layout. In recent times however, as design applications
have become more portable and power sensitive, power exploration and
smart design practices for optimizing power have taken centre stage.
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| PowerTheater 2006.3 Enhancements
Include Clock Power Management, Gate-Level Vectorless, Faster Vector
Analysis: PowerTheater 65, Sequence Design's flagship product for
RTL power estimation and management, includes enhanced clock power
estimation and reduction, as well as improvements to stimulus generation
and performance. . |
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| Sequence Design, has extended its
technology lead by adding the 22nd patent to the company's design-technology
portfolio. U.S. Patent No. 7,117,457 has been granted to Jerry Frenkil,
Sequence's general manager, Silicon Business Unit, CTO and VP of R&D,
and describes a new "current scheduling system and method for
optimizing MTCMOS (Multi-Threshold CMOS) designs." |
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| Industry Events
Calendar |
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with FPGA/PLD Design Conference
January 25-26, 2007, PACIFICO YOKOHAMA, Kanagawa, Japan. More
information, |
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Visit Sequence
Design at VLSI Design Conference 2007!
Don’t miss the VLSI Conference 2007, featuring 5 days
of in-depth presentations of various aspects of VLSI design,
electronic design automation (EDA), enabling technologies, and
embedded systems.
- Is your design power-sensitive?
- Do you compete on power specs?
Are you high-volume and packaging costs matter?
Would you like to learn more about power management from RTL
through GDS?
Visit Sequence Design at the D’Gipro booth. More information,
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India Semiconductor
Association highlights the importance of low power design as
a critical driver for the electronics industry
India Semiconductor Association (ISA) organised a panel discussion
on Low Power Design on December 12, 2006, at the Leela Palace
Bangalore, in collaboration with Cadence Design Systems, Inc.
(NASDAQ: CDNS)
The topic of the panel discussion was “Accelerating Low
Power Design: The New Industry Imperative”. Representatives
from the world’s leading semiconductor, foundry, and Intellectual
Property (IP) and Electronic Design Automation (EDA) companies
highlighted the need for low power design in today’s highly
connected world. |
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Sequence Design, the EDA leader in power-aware SoC design solutions,
recently hosted more than 80 Japanese IC designers, representing
23 leading Japanese electronics companies, at its fourth low-power
design seminar in Tokyo. Co-sponsored by Cadence, HP, and NEC
System Technology, the daylong event addressed major problems
affecting chip design for consumer, mobile, and highly integrated
devices. The focus was on four areas: predicting power consumption
early in the design cycle, reduction of switching power consumption,
reduction of leakage power, and efficient power-grid design.
For more information, |
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Industry Leaders Detail Ins & Outs Of Doing Business In India
Sequence Design president and CEO Vic Kulkarni is set to moderate
an EDAC panel Tuesday, Nov. 28 on "Doing Business in India." |
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| Sequence Design accelerates
the ability of SoC designers to bring high-performance, power-aware
ICs quickly to market. Sequence's low power flow software solutions
give customers the competitive advantage necessary to excel in aggressive
technology markets, despite the demanding complexity and time-to-market
issues of nanometer design. Sequence serves over 150 customers worldwide,
in application segments such as consumer, wireless, mobile computing,
multimedia, cell phones, digital cameras, network-on-chip processors,
and other power-sensitive markets. Sequence has worldwide development
and field-service operations and is privately held. Please see . |
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© Copyright 2007 Sequence Design,
Inc. Cool by Design, CoolPower, CoolTime, PowerTheater, PhysicalStudio
are trademarks of Sequence Design, Inc. All trademarks mentioned herein
are the property of their respective owners.
Sequence Design, Inc. | 469 El Camino Real | Santa Clara CA 95050
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