CoolCircuit July '06: Sequence Powers Up For DAC

	SEQUENCE POWERS UP FOR DAC - BOOTH 1614
	AZUL SYSTEMS FINDS CONVERGENCE WITH SEQUENCE COOLTIME
	LOW-POWER STARTUP GIQUILA UNLEASHES SEQUENCE COOLTIME ON NEXT-GEN 90NM 3D GRAPHICS CHIP
	SEQUENCE BOOSTS USABILITY, PERFORMANCE OF POWER-GRID INTEGRITY SOLUTION
	SEQUENCE, ARITHMATICA PARTNER TO ADVANCE SOC LOW-POWER DESIGN
	POWER-AWARE ESL-BASED DESIGN

Will the Real Leader for Low-Power EDA Solutions Stand Up?

Those walking the long aisles of DAC this year may find themselves experiencing more than just a touch of deja vu. Of course, there will be a few new companies, a few new faces, but carrying over will be an overwhelming focus on the critical importance of low-power design.

Recognizing this, EDA vendors will be claiming leadership in low-power. They will tell customers they have the best solution, something new and different, that will solve all problems. But is that what really matters?

Vic Kulkarni, President and CEO, Sequence Design

We see power emerging as a key competitive advantage in portable and consumer markets, driven by the increasing importance of battery life in a wide spectrum of products. For high-volume consumer/computer/multimedia applications, costs of IC packaging, system packaging, and cooling track strongly with power dissipation. At 90 nm and below, power becomes even more critical. Without proper power management and power-grid design, there can be catastrophic functional failures, timing problems, and signal-integrity issues. This dictates a complete power signoff, otherwise NREs go up; market windows are missed; market share decreases; and startups sink or giants stumble.

At Sequence, we recognized early on that power would be a significant barrier to design success, and invested R&D resources in building a rock-solid patent portfolio and tools that addressed the right problems at the right time. For example, PowerTheater remains the only RTL analysis and management solution, and was preferred for power management by nearly 70% of respondents in an ESNUG user survey late last year.

Customers from around the world in various application segments have been telling us about the challenges they are facing in terms of managing power issues as early in the design phase as possible. At this year's DAC, our Silicon Aware PowerTheater 65 debuts, with tremendous new features for multi-voltage islands, mixed voltage threshold, power gating, and clock gating. PowerTheater 65's capabilities include accurate RTL power analysis closely correlated to actual silicon; power management tools that allow designers to reduce power at RTL using "what-if" scenarios and make early tradeoffs at the architectural level; power vector forward technology to select vectors for downstream analysis, feeding them to later stages of the design cycle for gate-level verification and voltage-drop analysis; and gate-level power verification, preventing power creep.

Sequence will also be demonstrating its Cool products, consisting of CoolTime, CoolPower, and CoolCheck. CoolTime / CoolPower are concurrent and SI-aware, enabling fast design closure times by preventing time-consuming iterations between separate timing, SI, and power analysis and optimization tools. These products also help manage power through a variety of reduction techniques. At DAC, Sequence will introduce clock power and voltage island analysis, two new options for CoolPower / CoolTime for dynamic power reduction.

Also on display will be CoolCheck, the first and only formal power grid verification tool, enabling designers to check 100% of all power grid connections, rapidly detecting errors that both static and dynamic voltage-drop solutions fail to find. Our award-winning, highly accurate Columbus series of extraction products feature new, high-capacity, user-friendly viewers. This same technology is used as the foundation technology in Cool product line making them the most accurate analysis tools for timing, signal-integrity, electro-migration and dynamic voltage-drop effects.

Sequence continues to define "leadership" in low-power design. This is evidenced by customer satisfaction at more than 140 sites worldwide, a longtime commitment to serious science resulting in true breakthrough products, and beneficial relationships with foundries and other EDA companies to insure interoperability and ease of use.

We look forward to seeing you at DAC and providing you with a sense of what lies ahead for you in partnership with us. Together, there is nothing we cannot do.

Vic Kulkarni
President and CEO
Sequence Design, Inc.

Azul Systems Finds Convergence With Sequence CoolTime

Azul Systems, pioneer of the industry's first network attached processing solution, has adopted low-power EDA leader Sequence Design's CoolTime to reduce leakage power in its massive SoCs without negatively impacting performance.

"What do you leave on the table, power or performance?" asked Paul Koike, Senior Director, Silicon Engineering at Azul. "We needed a tool to reduce leakage and fix all clock-slowing crosstalk at the same time - the only one that can handle all that and more is Sequence's CoolTime." More...

Low-Power Startup GiQuila Unleashes Sequence CoolTime On Next-Gen 90nm 3D Graphics Chip

Innovative fabless startup GiQuila, specializing in low-power design for next-generation portables, has achieved 90nm success using Sequence Design's CoolTime for timing and signal integrity.

The company's first 90nm tapeout is a multimedia, 3D graphic chip with multiple hierarchies and clock domains according to GiQuila CEO, Mike Cai. "We quickly achieved a successful tapeout with Sequence on this challenging project," Cai said. "They were on top of this project during our tapeout time, and resolved all of our engineering issues quickly and effectively." More...

Sequence expects to turn profit

Sequence expects to broaden its reach through partnerships with solution providers such as CoWare and Forte and agreements with custom consulting and design consulting firms using its tools.

"We have been making steady progress in our operating model in the last four years to march towards GAAP profitability this year," said Vic Kulkarni, president and CEO, Sequence Design Inc. (Santa Clara, Calif.), in a statement. "This is being helped by a specific surge in PowerTheater in the emerging wireless and mobile computing segments. Also, the much-awaited 90-nm design starts are happening, creating demand for our physical analysis and optimization products." More...

Sequence Design India Expands Operations

Sequence Design, a Silicon Valley leader in EDA software used by chip designers to reduce power in portable and wireless devices, has added two new technical executives, one in Applications and the other in R&D Operations, to its staff here while expanding research and product development activities in India.

Sequence has also ramped up hiring of R&D and field application engineers in its new facility located in the Logix Technopark, Sector 127 area. By investing more than Rs 5 Crores annually, the company has quickly turned its Noida operation into one of its four global "Centers of Excellence," joining like facilities in Santa Clara, Calif.; Westford, Mass.; and London, England. To continue its growth in India, Sequence has attracted top talent from prestigious IITs, Jadavpur University, Delhi College of Engineering, BITs, and prominent U.S. and European universities due to its commitment for advanced R&D and IP creation in India. More...

Sequence TAB Expands in India

Sequence Design's Center of Excellence in India has announced the addition of Professor M. Balakrishnan, an academic and luminary at IIT Delhi, to the Sequence Technical Advisory Board (TAB).

"As our opportunities grow in India and throughout Asia we believe it is important to globalize our TAB to focus on specific markets," said Vic Kulkarni, Sequence president and CEO. "We are very pleased to welcome Professor Balakrishnan into the Sequence family." More...

Sequence Boosts Usability, Performance Of Power-Grid Integrity Solution

Sequence Design, EDA's power-aware SoC design technology leader, has released new versions of CoolTime and CoolCheck for complete power-grid verification of the most advanced SoC designs, with improved usability, analysis, and optimization features to minimize set-up times and maximize user productivity. These usability improvements have dramatically improved the time it takes to achieve design closure by making it much easier to understand and debug results, particularly in IOs where nets are virtual, existing in GDS, but not in LEF. More...

Sequence, Arithmatica Partner To Advance SoC Low-Power Design

Sequence Design announces that Arithmatica, Inc. has joined its In-Sequence Technology Partner Program, permitting the two companies to significantly advance SoC low-power design technologies and methods. The In-Sequence Program promotes technology advances for power-aware design flows, modeling accuracy, EDA interoperability and research through the alignment of technology partners and academia.

"Working together lets us ensure SoC designers can efficiently and confidently use both CellMath, for datapath, and PowerTheater, for a variety of intellectual property (IP) blocks and full chip, to achieve significant power improvements," said Tony Curzon Price, Arithmatica CEO. More...

Power-aware ESL-based design

Leading systems and semiconductor companies are driving a move to electronic system-level (ESL) design. They now have the ability to create extremely complex systems from high-level C/C++ algorithms with high quality of results (QoR) in less time by incorporating products such as Forte's Cynthesizer™ into their design flows. As each month passes, more and more success stories of working silicon are being shown to the public. This is testament to the quality of the high-level synthesis tools being used as well as the ESL flow achieving "critical mass." More...

Industry Events Calendar
	Sequence Powers Up For DAC - Booth 1614 - Moscone Center, San Francisco - July 24-28, 2006 Sequence Design will unveil a host of new technologies for low-power design at this year's DAC, headed by its new Silicon Aware PowerTheater 65, an RTL power analysis and management solution targeted to address the challenge of designing at 65nm and below. "Power is an architectural issue that must be addressed early in the design cycle to achieve SoC power goals," said Vic Kulkarni, Sequence president and CEO. "PowerTheater 65 features a comprehensive set of Silicon-Aware capabilities for low-power RTL design and full-chip power management, even at 65nm. It highlights an exciting slate of new low-power technology we look forward to sharing with customers at this year's DAC." Demos of all Sequence products and their implementation in a complete power-integrity flow will be available at DAC by advance registration.

	Sequence Low-Power Design Seminar Coming to Bangalore on August 30th Sequence Design, EDA's power-aware SoC design technology leader, is taking its popular low-power design seminar to Bangalore for the first time on Aug. 30, 2006. The seminar will be held at: The Taj Residency, 41/3 M G Road, Bangalore, India Sequence presentations and invited speakers will focus on four areas: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design. Industry-specific information on low-power design for wireless will be presented.

	Sequence Takes Low-Power Message To Top Korean Designers Sequence Design, EDA's power-aware SoC design technology leader, set an attendance record at a recent low-power design seminar in Seoul attended by scores of top designers representing 18 major Korean semiconductor companies. Co-sponsored by HP and Sequence's Korean distributor, DavanTech, the daylong seminar addressed major problems affecting chip design for consumer, mobile, and highly integrated devices. Sequence presentations and invited speakers focused on four areas: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design. More...

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. The company was named by Reed Electronics as one of the top 10 companies to watch in the electronics industry, and was recently selected as one of high-tech's Top 100 companies by siliconindia magazine. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.

© Copyright 2005 Sequence Design, Inc. Cool by Design, CoolPower, CoolTime, PowerTheater, PhysicalStudio are trademarks of Sequence Design, Inc. All trademarks mentioned herein are the property of their respective owners.
Sequence Design, Inc. | 469 El Camino Real | Santa Clara CA 95050

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