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Great seeing so many of you at DAC! Talking with customers
and colleagues there, it is clear that power remains a
major focus for designs below 90nm. So it was very gratifying
to see the enthusiastic response to Sequence's "Design
For Power" (DFP) initiative we rolled out at the
show.
DFP represents a holistic approach to power, enabling
power exploration from the architectural level through
physical implementation, reducing power while preventing
power problems in timing, SI, and power grid design, with
our unique silicon-aware design techniques. Customers
already employing Sequence's DFP Flow are reporting RTL
power reduction of up to 50 percent, a 50 percent speedup
in design closure times, and leakage power reduction of
up to 1,000X.
The DFP Flow comprises PowerTheater for RTL power analysis
and reduction, with new PowerTheater-Explorer for power
visualization and debug. Accelerated design closure, power
reduction, and power-grid integrity is supplied by the
company's CoolProducts family, now with power gating analysis
and simultaneous switching noise options. The award-winning
Columbus extraction engine provides statistical corner
parasitics for significantly increased margin in the DFP
flow.
We have posted a demo on the home page that describes
this exciting technology in depth which I encourage you
to check out, or contact us directly for more information.
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| Sequence Design, the EDA leader
in power-aware SoC design solutions, announced its CoolTime-PGA (Power
Gating Analysis) will be added to the Japanese Semiconductor Technology
Academic Research Center (STARC) advanced design flow, STARCAD-CEL.... |
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Pairing Provides High-Level Optimization
Of Performance, Area, Power
NEC System Technologies, Ltd.
(NEC-ST) has joined the In-Sequence Technology Partner Program, promoting
EDA interoperability and advanced design methodologies.....
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| For its high-performance mixed-signal
designs, SANYO Semiconductor Co., Ltd. has signed a long-term agreement
to use Sequence Design's Columbus-AMS as its fast, accurate extraction
engine.... |
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| Key Stream Corporation,
designers of low-power wireless LAN chipsets, announced they are using
Sequence Design's PowerTheater to reduce power "when it counts,"
early in the design cycle, at RTL..... |
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As
semiconductor devices evolve toward faster speeds and smaller features,
it becomes increasingly difficult to ensure design margins sufficient
enough to meet device performance targets, and increasingly more
important to set the best possible margins to derive the full potential
of device performance.. |
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A funny thing
happened on the way to the "everything-is-handheld" world
of computing and communications: turns out Moore's Law doesn't apply
to batteries. While transistor counts are still doubling roughly
every 18 months, the same progress in battery life takes more than
five years... |
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It’s
true that the RTL design flow is largely commoditized. Yet, EDA
vendors do still manage to come up with at least incremental gains
for their tools and flows. If you’re in search of time/cost
savings, greater productivity, more efficient and accurate modeling,
or any of a number of enhancements, gold could be laying in wait
for you somewhere on the DAC show floor. .... |
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When NXP Semiconductors
started to use advanced low-power IC design techniques, it was in
for a surprise. "In some cases, we have experienced a twofold
productivity drop for the implementation phase," said Hervé
Menager, design and technology officer at NXP.... |
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Attack the
challenges of low power design holistically, from RTL to GDS. Manage
and reduce power. Avoid power problems. The only comprehensive tool
suite, with advantages for managers, for SoC architects and designers,
and for the physical implementation team: Design for Power with
Sequence.... |
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Sequence Design
announced PowerTheater-Explorer, an innovative option to the industry's
premier RTL power analysis engine, PowerTheater, that adds state-of-the
art power visualization and debug capabilities for fast, interactive
power reduction.... |
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Automated
Approaches Quicken Power Signoff, Reducing the Time for Critical
Analysis Steps From a Week to an Hour
A pair of vexing SoC design issues - Power Gating Analysis (PGA),
and Simultaneous Switching Noise (SSN) - are now being addressed
by low-power leader Sequence Design's CoolTime with automated analysis
capabilities that enable faster, more accurate power signoff. The
new PGA and SSN capabilities address critical design issues in low-power
wireless and high-speed interface designs, such as DDR. .... |
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Sequence Design
announced upgrades for its Columbus parasitic extractors, aimed
at high-frequency design, 65nm characterization, and analysis of
simultaneous switching noise (SSN). .... |
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| Industry Events
Calendar |
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Low-Power Leader Spotlights Complete "DFP" Flow,
Advanced Power-Management And Extraction Technologies
Sequence Design is unveiling the EDA industry's most comprehensive
suite of tools for power-aware design at this year's DAC with
its Design For Power (DFP) Flow, attacking the challenges
of low-power design holistically, from RTL to GDS. Customers
already employing Sequence's DFP Flow are reporting RTL power
reduction of up to 50 percent, a 50 percent speedup in design
closure times, and leakage power reduction of up to 1,000X.....
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Sequence
and Mentor Graphics Collaborate on ESL Power Exploration Flow
Sequence Design, the EDA leader
in power-aware SoC design solutions, announced a collaborative
effort with Mentor Graphics that has resulted in an integrated
electronic system level (ESL) power exploration flow. This
project stems from Sequence's membership in the Mentor Graphics'
OpenDoor® partnership program..... |
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Sequence Design announced that Concept Engineering has joined
its In-Sequence Technology Partner Program, promoting EDA
interoperability and advanced design methodologies. Concept
Engineering is integrating its visualization technology into
Sequence's low-power analysis and optimization tools to improve
exploration and debug capabilities..... |
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Sequence
Design announced DeFacTo Technologies has become the newest
member of its In-Sequence Technology Partner Program, promoting
EDA interoperability and advanced design methodologies. The
first collaboration between the companies is the integration
of DeFacTo's scan insertion tool, to be released later this
year, and Sequence's PowerTheater. |
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Sequence
Design, the EDA leader in power-aware SoC design solutions,
announced it has become an Advanced IBM Business Partner,
and its Columbus-AMS extraction technology is now validated
as "Ready for IBM Technology" (RFIT) for IBM's industry-leading
BiCMOS and CMOS-RF process technologies. . |
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Sequence
Design accelerates the ability of SoC designers to bring high-performance,
power-aware ICs quickly to market. Sequence's low power flow software
solutions give customers the competitive advantage necessary to
excel in aggressive technology markets, despite the demanding complexity
and time-to-market issues of nanometer design. Sequence serves over
150 customers worldwide, in application segments such as consumer,
wireless, mobile computing, multimedia, cell phones, digital cameras,
network-on-chip processors, and other power-sensitive markets. Sequence
has worldwide development and field-service operations and is privately
held. Please see . |
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© Copyright
2007 Sequence Design, Inc. Cool by Design, CoolPower, CoolTime,
PowerTheater, PhysicalStudio are trademarks of Sequence Design,
Inc. All trademarks mentioned herein are the property of their respective
owners.
Sequence Design, Inc. | 469 El Camino Real | Santa Clara CA 95050
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