CoolCircuit June '08

	SEQUENCE DESIGN'S ELECTRONIC DESIGN EDITORIAL VIDEO FROM DAC 2008
	SEQUENCE DESIGN'S EDACAFE EDITORIAL VIDEO FROM DAC 2008
	GARY SMITH DISPELS EDA 'FEAR, UNCERTAINTY, DOUBT'
	WHAT COLOR IS YOUR RTL? SEQUENCE AT DAC, BOOTH 2100
	DAC POWER EXHIBITOR FORUM PRESENTED BY SEQUENCE DESIGN, INC.
	LOW POWER COALITION WORKSHOP - ADVANCES IN LOW POWER DESIGN FOR CIRCUITS AND SYSTEMS
	SEQUENCE SIGNS CHELSIO, SETS MILESTONE: 100TH POWERTHEATER CUSTOMER
	TZERO DRIVES LOW-POWER WITH SEQUENCE
	SI2 ANNOUNCES BOARD OF DIRECTORS FOR 2008-2009
	SEQUENCE CHAPTER IN NEW PFI BOOK DETAILS EARLY POWER ANALYSIS TIPS
	STARC ADDS SEQUENCE LOW-POWER TOOLS TO ADVANCED DESIGN FLOW
	SEQUENCE DESIGN'S POWERARTIST DELIVERS FASTEST AUTOMATED RTL POWER REDUCTION: UP TO 50% CUT IN MINUTES
	INDUSTRY GADFLY: "MY CHEESY MUST SEE LIST FOR DAC 2008"
	WHAT TO SEE @ DAC 2008
	45TH DAC TAKES THE SOC METHODOLOGY PLUNGE
	TEN-STEP PROGRAM - SEQUENCE POWERARTIST IDENTIFIES WAYS TO REDUCE POWER
	SEQUENCE POWERARTIST PROMISES FAST RTL POWER REDUCTION
	DESIGN FOR LOW POWER: SEQUENCE OFFERS TO AUTOMATE WHAT THE EXPERTS DO BY HAND
	DMP SLASHES POWER 50% IN NEW 3-D GRAPHICS PROCESSOR IP CORE "PICA200" WITH SEQUENCE POWERTHEATER
	AXELL REDUCES POWER, INCREASES PRODUCTIVITY WITH SEQUENCE'S POWERTHEATER

Customer Success

Technology

Events

You saw this phrase a lot if you spent any time at our DAC booth. It's the theme we used to launch our newest power-reducing technology, PowerArtist. More than 60% of respondents to a recent survey listed power analysis and reduction as their biggest design headache.

PowerTheater proved the value of analyzing power at RTL, and PowerArtist takes this concept to the next level by automatically reducing power up to 50% in just minutes in a million-plus gate block at this early stage of the design. Alternatively, users can call up changes recommended by PowerArtist in a powerful new GUI that flags problem areas and guides them through a series of manual edits.

PowerArtist is able to achieve these dramatic savings by focusing on the three biggest power-hungry areas in today's typical SoC:

Memory - 20-50% of total power consumption
Clock - 30-60% of total power consumption
Datapath - 20-30% of total power consumption
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Vic Kulkarni, President and CEO, Sequence Design

Sequence Signs Chelsio, Sets Milestone: 100th PowerTheater Customer

Sequence Design, the EDA leader in Design for Power (DFP) solutions, today announced it has signed its 100th PowerTheater customer, 10 Gigabit Ethernet pioneer Chelsio Communications. Chelsio is planning to use Sequence's PowerTheater in the design of its advanced scalable, high-performance 10Gb Ethernet unified wire engine ASIC, enabling simultaneous support of iSCSI, RDMA and TCP/IP socket applications.
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Tzero Drives Low-Power with Sequence

Sequence Design, the EDA leader in Design for Power (DFP) solutions, announced that Tzero Technologies, the leader in Ultra Wideband (UWB) technology and wireless video products, has adopted PowerTheater as a key component in its low-power design flow for high-performance, ultra wideband silicon.
"We have identified significant power savings using PowerTheater," said Ravi Aripirala, Ph.D, Tzero's Director of ASICs. "The completeness and accuracy of its analysis combined with easy to use visualization tools make PowerTheater a valuable part of our flow."
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STARC Adds Sequence Low-Power Tools To Advanced Design Flow

Sequence Design announced that its PowerTheater and CoolTime low-power tools have been integrated into the latest release of the Japanese Semiconductor Technology Academic Research Center (STARC) advanced design flow, STARCAD-CEL Version 2.0.
STARCAD-CEL Version 2.0, addressing the challenges of very advanced process technologies including 65nm and 45nm, has been updated to emphasize low-power design, particularly RTL power analysis and reduction, and power integrity at physical implementation. The STARCAD-CEL Version 2.0 design methodology is shared by the leading Japanese semiconductor companies that comprise STARC's membership as a standard digital design platform.
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DMP Slashes Power 50% In New 3-D Graphics Processor IP Core "PICA200" With Sequence PowerTheater
DMP, the world-class leader of 3-D graphics solutions, headquartered in Tokyo, has achieved a 50 percent reduction in power for their latest offering using Sequence Design's PowerTheater.
DMP's PICA200 is an advanced, fully customizable multiprocessor design optimized for consumer applications including mobile devices, and has unmatched 3-D graphics capabilities while reducing overall system memory requirements.
"Power usage is an important consideration for these devices," said Wataru Yokozeki, Business Development Director of DMP. "PowerTheater's ability to analyze power at a high level has proven to be immensely valuable by allowing us to optimize our architecture to maximize power reduction. We also found its vector and peak power analysis particularly useful during the design of this core, we could eliminate power-bugs using these capabilities."
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Axell Reduces Power, Increases Productivity With Sequence's PowerTheater
Axell Corporation, an emerging Japanese multimedia chip supplier, has selected Sequence Design's PowerTheater for precision power calculations at RTL, routinely reducing power consumption by as much as 20 percent according to Kazunori Matsuura, Engineering Group Director, Axell Corporation. Axell has recently taped out a complex graphic chip comprising multi million gate devices with PowerTheater.
"With a very precise measurement of power at RTL we could determine power budgets and make packaging decisions early in the design cycle which reduces costs significantly," Matsuura said. "In addition to its outstanding accuracy at RT level, PowerTheater was also quite easy to use. Designers could visualize and resolve power-related problems quickly."
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Sequence Design’s Electronic Design Editorial Video from DAC 2008

Sequence Design's President and CEO, Vic Kulkarni, paints the picture on his company's new PowerArtist tool, which takes a uniquely graphical – and colorful – approach to RTL power reduction for clocks, memory, and datapath
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Sequence Design’s EDACafe Editorial Video from DAC 2008

Sequence Design's President and CEO, Vic Kulkarni, discusses the company's new RTL power reduction tool, PowerArtist
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Sequence Chapter In New PFI Book Details Early Power Analysis Tips

Sequence Design's Tom Miller, Vice President and Head of R&D, Front-End Products, is one of the featured authors in a new book, "A Practical Guide to Low-Power Design - User Experience with CPF," that has been released by the Power Forward Initiative (PFI). The book can be downloaded free of charge at www.powerforward.org.
The Sequence chapter, "Early Power Analysis with CPF," details how the biggest power reductions can be achieved during architectural tradeoffs and describes multiple techniques for power analysis and optimization along with real-world examples of these approaches in action.
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45th DAC Takes The SoC Methodology Plunge

Come to Anaheim this June to get up to speed on the latest in ESL, physical design, analysis technologies, and verification, with a slant toward hands-on tutorials.
DAC is the place to be this year for low-power designers, with tutorials, paper sessions, and several workshops delving into the how-to's of designing low-power SoCs. Minimizing SoC power consumption has become a prime design goal, especially for multiprocessor SoCs, where peak temperature limits are of high concern. Sequence Design is planning to show its PowerArtist tool, which focuses on power reduction at RTL in three key areas: clocks, memory, and datapath. The tool's analysis engines examine the design's RTL code, prioritize design hotspots, and deliver power reduction in one of two ways. It can operate in automatic mode or guide the user through manual edits within a graphical user interface.
PowerArtist can be integrated with all design flows, including synthesis and formal verification. It's also compatible with OpenAccess databases through its open API. Pricing starts at $220,000 for a one-year time-based license.
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Ten-Step Program - Sequence PowerArtist Identifies Ways to Reduce Power

Power has become a key design consideration for SoCs in pretty much any application. We've looked at some ways of reducing power in past articles, largely at a high level. We continue here with a specific look at some techniques that can be identified by a new tool from Sequence called PowerArtist. This tool takes ten specific steps to identify ways to reduce power, although only a couple of them are automatically implemented. Most of them may take some engineering evaluation to decide whether to implement, and, if so, exactly how to do them, so those techniques are so-called "guided" ones, in that the tool guides the engineer towards power savings opportunities
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Sequence Design's PowerArtist Delivers Fastest Automated RTL Power Reduction: Up To 50% Cut In Minutes

Sequence Design today introduced PowerArtist™, offering the industry's fastest automated RTL power reduction - 10 to 50 percent or more depending on the design - in just minutes on a million-plus gate block. Unlike approaches limited by design size, PowerArtist has run on a 15M gate design in four hours within a 12GB footprint.
Built upon the foundation of proven Sequence RTL DFP (Design For Power™) accurate power analysis technology, PowerArtist focuses on trimming power in three key areas: Clock, Memory, and Datapath at RTL where designers have maximum opportunities for power reduction. The power savings are over and above those achieved during synthesis. Next-generation engines examine the RTL code, prioritize power reductions, and either maximize power savings automatically or guide the user through manual edits within a powerful graphical environment, Sequence's new PowerCanvas™ GUI. The RTL changes preserve the original RTL formatting by only making precise, surgical changes to the code.
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Sequence PowerArtist promises fast RTL power reduction

Claiming to achieve 10 to 50 percent power reductions on million-gate blocks in minutes, Sequence Design is rolling out PowerArtist, an RTL power reduction tool. It provides a combination of manual and automated capabilities to reduce clock, memory, and datapath power consumption.
Sequence today is best known for its power analysis tools, including PowerTheater, which works at the register-transfer level. PowerArtist uses the same analysis technology as PowerTheater, but adds the ability to make power reductions. PowerArtist takes in RTL code and finds opportunities for power reduction. Depending on the optimization it's running, it can automatically rewrite power-optimized RTL, output synthesis constraints, or guide the user through a manual RTL rewrite.
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Design for low power: Sequence offers to automate what the experts do by hand

One of the known facts about power reduction in SoC design is that the earlier in the design flow you can make reductions, the more effective they are likely to be. Architectural changes can make integer-factor differences in power, where major reworks during physical design may only save a few per cent. Another truism is that there is no substitute for experience. Some architects and RTL designers seem to have a built-in block-level power analyzer in their brains, and to instinctively implement things in very energy-efficient ways.
Sequence Design, already a leader in post-synthesis power analysis tools, has pondered these points, and come up with a tool suite-PowerArtist-that attempts to automate some of those best practices that expert designers use during RTL design.
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Industry Events Calendar

	What Color Is Your RTL? Sequence at DAC, Booth 2100 PowerArtist, the latest in a long line of technically advanced power-reduction tools from Sequence Design, takes center stage at this year's DAC as the company asks, "What color is your RTL?" "It's a serious question that SoC designers are grappling with," says Sequence President and CEO Vic Kulkarni. "PowerArtist provides a palette of new RTL power-reduction techniques that lets designers mix, blend and apply just the right touches to create their own masterpiece." ...More...

	Power Exhibitor Forum Presented by Sequence Design, Inc. Sequence's Jerry Frenkil, General Manager, Silicon Business Unit, CTO and VP of R&D discussed how Design for Power (DFP) has become essential for product success, especially in today's consumer driven battery powered market. This presentation will focus upon particular DFP methods and techniques, focusing on those deployed early in the design process when DFP can be most effective. In addition, the concept of power regression testing will be introduced as a means of tracking and controlling power consumption beginning at the earliest design phases and continuing through tapeout ...More...

	Low Power Coalition Workshop – Advances in Low Power Design for Circuits and Systems This workshop featuring Sequence Design’s Jerry Frenkil, General Manager, Silicon Business Unit, CTO and VP of R&D, will present the steps forward since the last Low Power Workshop at DAC 2007 and discuss future directions and end-user experiences with the technology developed and implemented so far. A selection of advanced tools that have been developed by some of the EDA companies will be presented to provide tangible progress in power-aware design ...More...

	What to see @ DAC 2008 by Gary Smith EDA Sequence Design and PowerArtist were selected as one of 25 companies and technologies on Gary Smith’s Must See List at DAC 2008 ...More...

	INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2008" Sequence PowerArtist does automated RTL power reduction "up to 50% cut". Ran on a 15 M gate design in 4 hours with a 12 GB footprint. "Power savings are over and above those achieved during synthesis." Ask for Preeti Gupta. Freebie: psychedelic pens? ...More...

	Gary Smith dispels EDA 'fear, uncertainty, doubt' Anahiem, Calif. -- Analyst Gary Smith challenged misconceptions about the semiconductor and EDA industries at the Design Automation Conference (DAC) here Sunday (June 8), and noted that EDA has reached a major inflection point. He also presented his top ten issues for 2008 and explained his "What to see at DAC" list. Smith spoke Sunday night (June 8) at the DAC General Chair's reception, an event introduced by Limor Fix, DAC 2008 general chair, and sponsored by SCDsource.com. The event also featured Mary Olsson, analyst at Gary Smith EDA, who spoke about 2008 as the "year of analog," and Bryan Lewis, analyst at Gartner Dataquest, who discussed ASIC and FPGA design starts. Smith also spoke at a panel session Monday. ...More...

	Si2 Announces Board of Directors for 2008-2009 The Silicon Integration Initiative (Si2) announces the election of their Board of Directors for the 2008-2009 term, as well as the place and time for the Annual Member/Guest Meeting. The new Corporate Board Member is: Sequence Design, represented by Mr. Vic Kulkarni, president & CEO. This new 10th position on the Board of Directors is reserved for an end-user company or EDA company whose annual revenue is less than $100M/year. ...More...

Sequence Design's Design For Power (DFP) solutions accelerate the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal-integrity software give customers the competitive advantage necessary to excel in aggressive technology markets. Sequence is an active participant in industry organizations advancing low-power design technologies such as the Power Forward Initiative and holds a seat on the board of Si2. Please see sequencedesign.com.

© Copyright 2008 Sequence Design, Inc. Cool by Design, CoolPower, CoolProducts, CoolTime, PowerArtist, PowerTheater, PhysicalStudio are trademarks of Sequence Design, Inc. All trademarks mentioned herein are the property of their respective owners.
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