CoolCircuit September '06: The Age of Enlightenment.

	SEQUENCE'S SILICON AWARE POWERTHEATER 65 TACKLES POWER EARLY AT RTL
	SEQUENCE, BLUESPEC TEAM TO OFFER USERS ESL DESIGN OPTIMIZED FOR PERFORMANCE, AREA, POWER
	THE AGE OF ENLIGHTENMENT. A CONVERSATION WITH VIC KULKARNI...
	SEQUENCE CTO JERRY FRENKIL TO SPEAK AT 4TH ANNUAL INTERNATIONAL SOC CONFERENCE
	SEQUENCE CLOCK POWER, VOLTAGE ISLAND ANALYSIS BESTS COMPETITION
	SEQUENCE LOW-POWER PRESENTATION HIGHLIGHTS SAME 2006

Insight on Design

Total power, leakage power, electromigration, and dynamic voltage drop provide the biggest pain points for SoC designers today, according to the majority of respondents to a survey we conducted at DAC this summer.

A very even distribution of 25% of the responses noted each of these 4 parameters as critical in design closure and signoff.

Process node migration statistics have been tracked by many analysts; this sample showed the highest growth rate at the 65nm process node even though the majority of designs are still thriving at 90nm.

Vic Kulkarni, President and CEO, Sequence Design

Low power seems to be on everybody's mind these days: the most frequently stated concern was achieving the power specs for their SoC (38%) followed by battery life (26%) IC packaging costs (15%) reliability (12%) and Yield (9%).

Today's designers are challenged with several criteria to manage power. The most popular techniques to manage power are: clock gating (24%); multi-Vt libraries (22%); power gating (15%); voltage islands (13%); and clock power optimization (13%) - (respondents were allowed to specify more than one technique).

More than 50% of the respondents manage power through both front end design and back end implementation efforts, resulting in equal product interest for Sequence Design's PowerTheater™ and CoolProducts™.

Regarding design elements, besides datapath and memory, around half of the designers canvassed used MPU / DSP cores and 44% designed / used analog blocks.

For most, the language of design still means Verilog, the language of choice for almost 50%, System Verilog with 20%, or VHDL with 9%. For higher level design, 16% reported designing in System C or C++; while commercial ESL tools were currently used by a scant 5% of respondents.

In conclusion, general comments from designers favored power management tools across the board, especially for RTL power analysis; accuracy; power estimation for emerging power techniques, visual power debug; wasted power detection; integrated tool flows; vectorless power estimation; power analysis tools that support power gating; and basically everyone would like to achieve faster results!

The survey results are based on 115 responses. The industry sectors most represented among survey respondents are wireless telecommunications (31%), portable electronics equipment (21%) and computer networking (27%).

If you have thoughts to share about these results or your own pain points, drop us a line at: sales@sequencedesign.com. Hope to hear from you soon.

Vic Kulkarni
President and CEO
Sequence Design, Inc.

Sequence, Bluespec Team To Offer Users ESL Design Optimized For Performance, Area, Power

EDA startups Sequence Design and Bluespec Inc. have entered into a partnership that aims to offer customers electronic system level (ESL) productivity combined with an ability to analyze architectures for performance, area and power. More...

Sequence Wows Bangalore Designers At Low-Power Seminar

Nearly 60 top Bangalore IC designers provided Sequence Design with an enthusiastic reception as the company held its first low-power design seminar in the booming high-tech center last week. There were attendees from 31 companies, including representatives from some of the city's biggest such as Intel, NVIDIA, Philips, Texas Instruments, and Cypress. Topics at the daylong seminar focused on four key subjects: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design. More...

The Age of Enlightenment. A Conversation with Vic Kulkarni...

Peggy Aycinena talks to Vic Kulkarni, CEO of Sequence Design about a range of topics not specific to the company, but on the larger subjects of globalization and the various trends associated with all of that. More...

Cadence moves to broaden power initiative

The Power Forward Initiative (PFI), launched by Cadence Design Systems to develop a common IC power description format, is announcing this week that three EDA vendors have joined the effort. But as PFI targets the IEEE, a second power standards effort launched at the July Design Automation Conference is charting a different route to standardization. More...

Sequence Extends EM And V-drop Analysis To Full-Custom Designs

Combining its award-winning Columbus-AMS extraction engine with electromigration and voltage-drop components from its CoolTime dynamic voltage-drop product, Sequence Design has created Speedview-AMS, the latest in a series of new tools for power-rail analysis. Speedview-AMS enables designers to diagnose EM and V-drop issues in full-custom designs. More...

Sequence Clock Power, Voltage Island Analysis Bests Competition

The Clock Power Analysis option enables significant reductions in clock network power, often the biggest component of dynamic power. Voltage Island Analysis lets users easily and quickly optimize islands, speeding design time and accuracy.

"The tribe has spoken, and they are demanding these huge additions to the Cool Products low-power design portfolio," said Sequence president and CEO, Vic Kulkarni. "We are leaving the competition in the dust with greatly improved performance paired with unequalled user friendliness." More...

Sequence's Silicon Aware PowerTheater 65 Tackles Power Early At RTL - Adds Mixed Voltage Capabilities

Addressing the complex issues of low-power design at 65nm and below is Sequence Design's Silicon Aware PowerTheater 65, the industry's first RTL power analysis and management solution with physical-design features to insure results that closely relate to real silicon.

"The stakes are being raised at 65nm," said Vic Kulkarni, Sequence president and CEO. "We have been working closely with key customers around the world to understand and address mission-critical issues of power management as they migrate their designs from 130 to 90 to 65nm. By offering early, accurate power analysis, closely correlated to silicon, PowerTheater 65 addresses SoC power-design challenges and speeds time to market for even the largest, most complex designs." More...

Industry Events Calendar
	Sequence Low-Power Presentation Highlights SAME 2006; Talk Describes Novel Method To Reduce Power-Switch Size Nearly 90% Sequence Design's Dr. Kyu-won "Ken" Choi, Senior Engineer and Technical Consultant, will be a featured speaker on low-power design during the ninth annual SAME 2006 Conference being held Oct. 4-5 in Sophia Antipolis, France. More...

	Sequence Sponsors MemCon Sept. 12-14 Sequence Design, EDA's power-aware SoC design technology leader, sponsored MemCon event, scheduled on Sept. 12-14 in Santa Clara, Calif. Held annually, MemCon addresses the business, technology, and system design strategies for semiconductor memory and storage. More...

	Sequence CTO Jerry Frenkil To Speak At 4th Annual International SoC Conference Sequence Design's Jerry Frenkil, CTO, Vice President and General Manager, Silicon Business Unit, will join a panel of experts addressing "EDA Challenges for Complex SoC and ASIC Designs" at the upcoming International SoC Conference & Exhibit, Nov. 1-2 in Newport Beach, Calif. For more information, Click Here.

	Sequence Brings Power-Aware Lineup To Taiwan's EDA&T Aug. 17-18 Sequence Design, EDA's power-aware SoC design technology leader, showcased its products at this year's EDA&T in Taipei, Aug. 17-18. Appearing with its distributor, Maojet, demos of all Sequence products and their implementation in a complete power-integrity flow were available. Highlights include the recently released Silicon Aware PowerTheater 65, CoolPower/CoolTime with multi-Vt and clock analysis options, and Speedview-AMS for faster full-custom extraction. More...

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. The company was named by Reed Electronics as one of the top 10 companies to watch in the electronics industry, and was recently selected as one of high-tech's Top 100 companies by siliconindia magazine. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.

© Copyright 2005 Sequence Design, Inc. Cool by Design, CoolPower, CoolTime, PowerTheater, PhysicalStudio are trademarks of Sequence Design, Inc. All trademarks mentioned herein are the property of their respective owners.
Sequence Design, Inc. | 469 El Camino Real | Santa Clara CA 95050

This message was sent by Sequence Design, Inc.
Click here if you prefer not to receive future e-mail from Sequence Design, Inc.