CoolCircuit October '07

	POWERTHEATER IN TOSHIBA FLOW
	SEQUENCE COOLPRODUCTS CHOSEN BY TEKTRONIX FOR POWER SIGNOFF
	HOW TENSILICA USES SEQUENCE'S POWERTHEATER TOOL
	DESIGN FOR POWER DEMO ON DEMAND
	NEW BOOK: CLOSING THE POWER GAP BETWEEN ASIC & CUSTOM, TOOLS AND TECHNIQUES FOR LOW POWER DESIGN CHINNERY, DAVID, KEUTZER, KURT
	AUTOMATING THE SSN VERIFICATION CHALLENGE
	ANALYZING DYNAMIC VOLTAGE DROP AT 90 NM AND BEYOND
	LOW POWER STANDARDS: ANYTHING YOU CAN DO...
	COOLEY DOES DAC
	DESIGN FOR POWER (DFP) SEMINARS
	SUPPLIERS FORUM & NETWORKING SERIES
	TWO-DAY COURSE ON LOW-POWER DESIGN AND TEST
	SEQUENCE AND FARADAY COLLABORATE ON INTEGRATED LOW POWER DESIGN FLOW
	FARADAY TECHNOLOGY ENHANCES POWERSMART(TM) DESIGN FLOW TO INCLUDE SEQUENCE'S RTL POWER ANALYSIS TOOL
	PERFORM DESIGN-FOR-TEST AND POWER MANAGEMENT AT THE RTL

Where are the biggest power savings in advanced designs? What tools and techniques deliver the biggest bang for the buck? Are there things we should be doing differently to maximize power efficiency? Can you show me some real-world success stories?

These are questions I hear a lot during customer visits and at our "Design For Power" (DFP) seminars, so I am sure many of you are wondering about the same things. In the past, design engineers could do little to control and manage power, but with today's tools, a variety of techniques can be used to reduce power 50% or more. Some proven techniques for power reduction include:

Architectural exploration: because 80% of power is committed before gate implementation
Power debug environment for user-controlled power reduction
Automated RTL power linting and advisories
Power saving techniques such as multi Vt, clock gating, voltage islands and power gating

More...

Vic Kulkarni, President and CEO, Sequence Design

PowerTheater in Toshiba flow

15 Design/Support Centers Companywide
Support and technical excellence are given the highest priority at Toshiba. Our design centers are strategically positioned around the world to support global customers by providing a high level of technical expertise in dealing with Toshiba ASIC technologies, design implementation and manufacturing methodologies.....More...

Sequence CoolProducts Chosen By Tektronix For Power Signoff

Tektronix, Inc., a leading, worldwide provider of test, measurement, and monitoring instrumentation, recently reviewed their power design and analysis needs and chose Sequence Design's CoolProducts for their accuracy, versatility, and outstanding support. Sequence's CoolProducts family - CoolTime, CoolPower, and CoolCheck - added key functionality to their design flow and reduced design closure times by preventing time-consuming iterations between separate timing, SI, power analysis and optimization tools.....More...

How TenSilica uses Sequence's PowerTheater tool

PowerTheater gave us what we needed to identify the architecture changes to reduce our power. It did this by making it easy to identify where the power was being consumed in the design at the RTL-level and where to make the necessary course corrections...... More...

Design for Power Demo on Demand

Sequence Design-For-Power Flow
Attack the challenges of low power design holistically, from RTL to GDS. Manage and reduce power. Avoid power problems. The only comprehensive tool suite, with advantages for managers, for SoC architects and designers, and for the physical implementation team: Design for Power with Sequence....More...

New Book: Closing the Power Gap between ASIC & Custom, Tools and Techniques for Low Power Design
Chinnery, David, Keutzer, Kurt

The demand for portable electronic devices is growing rapidly and, due in large part to the development of wireless communications, is expected to continue to grow. This demand has generated great interest in low power design, which initially focused on controlling dynamic power consumption..... More..

Automating the SSN verification challenge

Simultaneous Switching Noise (SSN) is the voltage fluctuation caused by the simultaneous switching of
groups of output chip I/O drivers that drive high slew rate signals. It has an impact on I/O and core
power supply lines and on signal lines, and is an increasingly important challenge for designs that
incorporate high performance interfaces, such as DDR. .... More..

Analyzing dynamic voltage drop at 90 nm and beyond

As VLSI technology scales to 90 nanometers and beyond, ASIC vendors increasingly see power grid integrity issues in their designs and in the field, for two primary reasons. First, deep-submicron geometries require lower power supply voltages, which reduce the chip's tolerance of noise (noise margin). Second, smaller geometries result in many more transistors per die..... More..

Low Power Standards: anything you can do...

lot of industry support around the Common Power Format,” said Pankaj Mayor, group director at Cadence, adding that the foundries TSMC and UMC had agreed to adopt CPF for the next versions of their reference flows..... More..

Cooley Does DAC
Sequence Featured in John Cooley's DAC Coverage...More..

Industry Events Calendar

Design For Power (DFP) Seminars

Akihabara Convention Center, Tokyo,
November 8, 2007
View Details

The Taj Residency, Bangalore,
September 19, 2007
View Details

Suppliers Forum & Networking Series

Santa Clara Convention Center, Santa Clara, CA, August 15, 2007

The Suppliers Forum & Networking Series showcases an array of suppliers presenting their products, services and solutions that address the business needs of fabless, IDM and OEM companies.... More..

Two-day Course on Low-power Design and Test

Hotel Green Park, Hyderabad, India, July 30-31, 2007

Power consumption of a CMOS circuit has emerged as an important design dimension in the nanometer era. The benefits of higher device density and increased clock rates for the modern VLSI system-on-chip (SOC) come at the cost of significantly increased power dissipation.... More..

Sequence and Faraday Collaborate on Integrated Low Power Design Flow

Sequence Design, the EDA leader in Design For Power (DFP) SoC design solutions, today announced that it has partnered with Faraday Technology Corporation to deliver an advanced low power design flow to Faraday’s ASIC design customers...... More...

Faraday Technology Enhances PowerSmart(TM) Design Flow to Include Sequence's RTL Power Analysis Tool

Faraday Technology Corporation , a leading ASIC and IP provider announced today that it has further enhanced the PowerSmart(TM) ultra-low power ASIC design flow to include a front-end tool, which allows designers to perform power trade-off and optimization at the RTL level. Sequence Design, a leader in providing advanced power-aware design tools, will be the supply partner of this tool.... More...

Perform Design-for-Test and Power Management at the RTL

A new methodology lowers the overall power budget during normal chip functioning while allowing a full power analysis of post-silicon test vectors.
There’s a consensus that power dissipation is a major concern in the design of modern chips. With today’s functionality and speed, power consumption ranks in the top three areas of concern for design managers. Because of the high power activity that’s required during manufacturing testing, power also is a source of concern for test and design-for-test (DFT) managers.....More...

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's low power flow software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.

© Copyright 2007 Sequence Design, Inc. Cool by Design, CoolPower, CoolTime, PowerTheater, PhysicalStudio are trademarks of Sequence Design, Inc. All trademarks mentioned herein are the property of their respective owners.
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